-
Notifications
You must be signed in to change notification settings - Fork 11
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
hal: renesas: Replace the BSP clock settings with new macros. #36
Conversation
6a74d76
to
33ff5b7
Compare
33ff5b7
to
4c68922
Compare
4c68922
to
6986e6e
Compare
Could you take a look? |
#define BSP_CFG_I3CCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_div, 0) | ||
#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk))) | ||
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1) | ||
#define BSP_CFG_U60CK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u64clk))) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@soburi , This seem to be a mistake
#define BSP_CFG_U60CK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u64clk))) | |
#define BSP_CFG_U60CK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u60clk))) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Thank you for catching.
I fixed it.
And found some mistakes in ra6m1, ra8d1 and ra8t1, also fixed.
#define BSP_CFG_LCDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(lcdclk), clk_div, 0) | ||
#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk))) | ||
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1) | ||
#define BSP_CFG_U60CK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u64clk))) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@soburi , ditto
#define BSP_CFG_LCDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(lcdclk), clk_div, 0) | ||
#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk))) | ||
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1) | ||
#define BSP_CFG_U60CK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u64clk))) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
@soburi , diito
6986e6e
to
c1d40bd
Compare
BSP_CFG_ADCCLK_DIV, BSP_CFG_ADCCLK_SOURCE, BSP_CFG_SDADCCLK_DIV and BSP_CFG_SDADCCLK_SOURCE are not referenced. Removed these. BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR was renamed and moved into `include/zephyr/drivers/clock_control` Signed-off-by: TOKITA Hiroshi <[email protected]>
Replace the includeed header file from `zephyr/dt-bindings/clock/ra_clock.h` to `zephyr/drivers/clock_control/renesas_ra_cgc.h` to standardize the macros. Signed-off-by: TOKITA Hiroshi <[email protected]>
To simplify the DeviceTree notation, we have introduced macros that derive BSP macro definitions from DeviceTree values. The clock settings were rewritten by it. Signed-off-by: TOKITA Hiroshi <[email protected]>
c1d40bd
to
7205e63
Compare
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM
@thaoluonguw , please take a look for this PR, related PR in Zephyr zephyrproject-rtos/zephyr#78365
@thaoluonguw |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
It's look good to me. Thank you.
@KhiemNguyenT |
To simplify the DeviceTree notation, we have introduced macros
that derive BSP macro definitions from DeviceTree values.
The clock settings were rewritten by it.