Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

hal: renesas: Replace the BSP clock settings with new macros. #36

Merged
merged 3 commits into from
Oct 1, 2024
Merged

hal: renesas: Replace the BSP clock settings with new macros. #36

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
05a3045
hal: renesas: Remove unused definitions
soburi Sep 12, 2024
d8eb7b3
hal: renesas: Replace the included header file
soburi Sep 13, 2024
7205e63
hal: renesas: Replace the BSP clock settings with new macros.
soburi Sep 12, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
41 changes: 14 additions & 27 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_clock_cfg.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,22 +1,20 @@
/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: BSD-3-Clause
*/
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>

#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_

#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))

#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))

#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
Expand All @@ -29,24 +27,13 @@
#else
#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz, 64MHz"
#endif
#define BSP_CFG_CLOCK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
RA_PLL_SOURCE_DISABLE)
#define BSP_CFG_ICLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_PCLKB_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_PCLKD_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_FCLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)

#define BSP_CFG_SDADCCLK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(sdadcclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_SDADCCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(sdadcclk), clk_div, 0)

#define BSP_CFG_CLKOUT_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
#define BSP_CFG_FCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 2)
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)

#endif /* BSP_CLOCK_CFG_H_ */
32 changes: 12 additions & 20 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_clock_cfg.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,21 +1,19 @@
/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>

#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_

#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))

#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))

#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
Expand All @@ -29,19 +27,13 @@
#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz, 64MHz"
#endif

#define BSP_CFG_CLOCK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))

#define BSP_CFG_ICLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_PCLKB_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_PCLKD_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)

#define BSP_CFG_CLKOUT_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)

#endif /* BSP_CLOCK_CFG_H_ */
67 changes: 25 additions & 42 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/bsp_clock_cfg.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,17 +5,15 @@
*/

#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>

#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_

#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))

#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))

#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */
Expand All @@ -27,49 +25,34 @@
#error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, and 20MHz"
#endif


#define BSP_CFG_PLL_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
#define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll)))
#define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
#define BSP_CFG_PLL_MUL \
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
#else
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_CLOCK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
RA_PLL_SOURCE_DISABLE)

#define BSP_CFG_ICLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_PCLKA_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_PCLKB_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_4)
#define BSP_CFG_PCLKC_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_4)
#define BSP_CFG_PCLKD_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_FCLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_4)

#define BSP_CFG_UCK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
#define BSP_CFG_CLKOUT_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
#define BSP_CFG_I3CCLK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_I3CCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_div, 0)
#define BSP_CFG_CECCLK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CECCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_div, 0)
#define BSP_CFG_CANFDCLK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CANFDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_div, 0)
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))

#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
#define BSP_CFG_PCLKA_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclka), div, 2)
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 4)
#define BSP_CFG_PCLKC_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkc), div, 4)
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 2)
#define BSP_CFG_FCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 4)

#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)))
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1)
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
#define BSP_CFG_I3CCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(i3cclk)))
#define BSP_CFG_I3CCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(i3cclk), div, 1)
#define BSP_CFG_CECCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(cecclk)))
#define BSP_CFG_CECCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(cecclk), div, 1)
#define BSP_CFG_CANFDCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(canfdclk)))
#define BSP_CFG_CANFDCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(canfdclk), div, 1)

#endif /* BSP_CLOCK_CFG_H_ */
50 changes: 18 additions & 32 deletions zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_clock_cfg.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,18 +5,15 @@
*/

#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>

#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_

#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)

#define BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \
(COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)))

#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))

#if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
#define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
Expand All @@ -30,39 +27,28 @@
#error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz and 64MHz"
#endif

#define BSP_CFG_PLL_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
#define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll)))
#define BSP_CFG_PLL_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 2)
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
#define BSP_CFG_PLL_MUL \
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0), \
DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
#else
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
#endif

#define BSP_CFG_CLOCK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src, \
RA_PLL_SOURCE_DISABLE)
#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))

#define BSP_CFG_ICLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_PCLKA_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_PCLKB_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_PCLKC_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_PCLKD_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
#define BSP_CFG_FCLK_DIV \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)
#define BSP_CFG_ICLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
#define BSP_CFG_PCLKA_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclka), div, 1)
#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
#define BSP_CFG_PCLKC_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkc), div, 1)
#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
#define BSP_CFG_FCLK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 2)

#define BSP_CFG_UCK_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
#define BSP_CFG_CLKOUT_SOURCE \
BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
#define BSP_CFG_UCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)))
#define BSP_CFG_UCK_DIV RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1)
#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
#define BSP_CFG_CLKOUT_DIV RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)

#endif /* BSP_CLOCK_CFG_H_ */
Loading