hal: renesas: Replace the BSP clock settings with new macros.

To simplify the DeviceTree notation, we have introduced macros that derive BSP macro definitions from DeviceTree values. The clock settings were rewritten by it. Signed-off-by: TOKITA Hiroshi <[email protected]>
zephyrproject-rtos · Oct 1, 2024 · 3dafd03 · 3dafd03
1 parent 38b2df8
commit 3dafd03
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diff --git a/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_clock_cfg.h b/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/bsp_clock_cfg.h
@@ -1,9 +1,9 @@
 /*
-* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
-* Copyright (c) 2024 TOKITA Hiroshi
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
 
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
@@ -14,7 +14,7 @@
 #define BSP_CFG_CLOCKS_SECURE   (0)
 #define BSP_CFG_CLOCKS_OVERRIDE (0)
 
-#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
+#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
 
 #if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
 #define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
@@ -27,19 +27,13 @@
 #else
 #error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz, 64MHz"
 #endif
-#define BSP_CFG_CLOCK_SOURCE                                                                       \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src,                   \
-					  RA_PLL_SOURCE_DISABLE)
-#define BSP_CFG_ICLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
-#define BSP_CFG_PCLKB_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_PCLKD_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
-#define BSP_CFG_FCLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_CLKOUT_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
+
+#define BSP_CFG_CLOCK_SOURCE  RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
+#define BSP_CFG_ICLK_DIV      RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
+#define BSP_CFG_PCLKB_DIV     RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
+#define BSP_CFG_PCLKD_DIV     RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
+#define BSP_CFG_FCLK_DIV      RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 2)
+#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
+#define BSP_CFG_CLKOUT_DIV    RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
 
 #endif /* BSP_CLOCK_CFG_H_ */
diff --git a/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_clock_cfg.h b/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/bsp_clock_cfg.h
@@ -1,8 +1,8 @@
 /*
-* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+ * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
 
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
@@ -13,7 +13,7 @@
 #define BSP_CFG_CLOCKS_SECURE   (0)
 #define BSP_CFG_CLOCKS_OVERRIDE (0)
 
-#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
+#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
 
 #if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
 #define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
@@ -27,19 +27,13 @@
 #error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz, 64MHz"
 #endif
 
-#define BSP_CFG_CLOCK_SOURCE                                                                       \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src,                  \
-					  RA_CLOCK_SOURCE_DISABLE)
+#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
 
-#define BSP_CFG_ICLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_PCLKB_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_PCLKD_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
+#define BSP_CFG_ICLK_DIV  RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
+#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
+#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
 
-#define BSP_CFG_CLKOUT_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
+#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
+#define BSP_CFG_CLKOUT_DIV    RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
 
 #endif /* BSP_CLOCK_CFG_H_ */
diff --git a/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/bsp_clock_cfg.h b/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/bsp_clock_cfg.h
@@ -13,7 +13,7 @@
 #define BSP_CFG_CLOCKS_SECURE   (0)
 #define BSP_CFG_CLOCKS_OVERRIDE (0)
 
-#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
+#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
 
 #if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 16000000
 #define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 16MHz */
@@ -25,49 +25,34 @@
 #error "Invalid HOCO frequency, only can be set to 16MHz, 18MHz, and 20MHz"
 #endif
 
-
-#define BSP_CFG_PLL_SOURCE                                                                         \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
-#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_1)
+#define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll)))
+#define BSP_CFG_PLL_DIV    RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 1)
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
 #define BSP_CFG_PLL_MUL                                                                            \
-	BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0),                            \
-			DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
+	BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0),                              \
+			   DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
 #else
 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
 #endif
 
-#define BSP_CFG_CLOCK_SOURCE                                                                       \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src,                  \
-					  RA_PLL_SOURCE_DISABLE)
-
-#define BSP_CFG_ICLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_PCLKA_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_PCLKB_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_4)
-#define BSP_CFG_PCLKC_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_4)
-#define BSP_CFG_PCLKD_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_FCLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_4)
-
-#define BSP_CFG_UCK_SOURCE                                                                         \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
-#define BSP_CFG_CLKOUT_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
-#define BSP_CFG_I3CCLK_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_I3CCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(i3cclk), clk_div, 0)
-#define BSP_CFG_CECCLK_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_CECCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(cecclk), clk_div, 0)
-#define BSP_CFG_CANFDCLK_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_CANFDCLK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(canfdclk), clk_div, 0)
+#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
+
+#define BSP_CFG_ICLK_DIV  RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 2)
+#define BSP_CFG_PCLKA_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclka), div, 2)
+#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 4)
+#define BSP_CFG_PCLKC_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkc), div, 4)
+#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 2)
+#define BSP_CFG_FCLK_DIV  RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 4)
+
+#define BSP_CFG_UCK_SOURCE      RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)))
+#define BSP_CFG_UCK_DIV         RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1)
+#define BSP_CFG_CLKOUT_SOURCE   RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
+#define BSP_CFG_CLKOUT_DIV      RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
+#define BSP_CFG_I3CCLK_SOURCE   RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(i3cclk)))
+#define BSP_CFG_I3CCLK_DIV      RA_CGC_CLK_DIV(DT_NODELABEL(i3cclk), div, 1)
+#define BSP_CFG_CECCLK_SOURCE   RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(cecclk)))
+#define BSP_CFG_CECCLK_DIV      RA_CGC_CLK_DIV(DT_NODELABEL(cecclk), div, 1)
+#define BSP_CFG_CANFDCLK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(canfdclk)))
+#define BSP_CFG_CANFDCLK_DIV    RA_CGC_CLK_DIV(DT_NODELABEL(canfdclk), div, 1)
 
 #endif /* BSP_CLOCK_CFG_H_ */
diff --git a/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_clock_cfg.h b/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/bsp_clock_cfg.h
@@ -10,11 +10,10 @@
 #ifndef BSP_CLOCK_CFG_H_
 #define BSP_CLOCK_CFG_H_
 
-#define BSP_CFG_CLOCKS_SECURE	(0)
+#define BSP_CFG_CLOCKS_SECURE   (0)
 #define BSP_CFG_CLOCKS_OVERRIDE (0)
 
-
-#define BSP_CFG_XTAL_HZ BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0)
+#define BSP_CFG_XTAL_HZ (RA_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(xtal), clock_frequency, 0))
 
 #if DT_PROP(DT_NODELABEL(hoco), clock_frequency) == 24000000
 #define BSP_CFG_HOCO_FREQUENCY 0 /* HOCO 24MHz */
@@ -28,39 +27,28 @@
 #error "Invalid HOCO frequency, only can be set to 24MHz, 32MHz, 48MHz and 64MHz"
 #endif
 
-#define BSP_CFG_PLL_SOURCE                                                                         \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), source, RA_PLL_SOURCE_DISABLE)
-#define BSP_CFG_PLL_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pll), div, RA_PLL_DIV_2)
+#define BSP_CFG_PLL_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pll)))
+#define BSP_CFG_PLL_DIV    RA_CGC_CLK_DIV(DT_NODELABEL(pll), div, 2)
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
 #define BSP_CFG_PLL_MUL                                                                            \
-	BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0),                            \
-			DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
+	BSP_CLOCKS_PLL_MUL(DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 0),                              \
+			   DT_PROP_BY_IDX(DT_NODELABEL(pll), mul, 1))
 #else
 #define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(0, 0)
 #endif
 
-#define BSP_CFG_CLOCK_SOURCE                                                                       \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkblock), sysclock_src,                  \
-					  RA_PLL_SOURCE_DISABLE)
+#define BSP_CFG_CLOCK_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(pclkblock)))
 
-#define BSP_CFG_ICLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(iclk), clk_div, RA_SYS_CLOCK_DIV_1)
-#define BSP_CFG_PCLKA_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclka), clk_div, RA_SYS_CLOCK_DIV_1)
-#define BSP_CFG_PCLKB_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkb), clk_div, RA_SYS_CLOCK_DIV_2)
-#define BSP_CFG_PCLKC_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkc), clk_div, RA_SYS_CLOCK_DIV_1)
-#define BSP_CFG_PCLKD_DIV                                                                          \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(pclkd), clk_div, RA_SYS_CLOCK_DIV_1)
-#define BSP_CFG_FCLK_DIV                                                                           \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(fclk), clk_div, RA_SYS_CLOCK_DIV_2)
+#define BSP_CFG_ICLK_DIV  RA_CGC_CLK_DIV(DT_NODELABEL(iclk), div, 1)
+#define BSP_CFG_PCLKA_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclka), div, 1)
+#define BSP_CFG_PCLKB_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkb), div, 2)
+#define BSP_CFG_PCLKC_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkc), div, 1)
+#define BSP_CFG_PCLKD_DIV RA_CGC_CLK_DIV(DT_NODELABEL(pclkd), div, 1)
+#define BSP_CFG_FCLK_DIV  RA_CGC_CLK_DIV(DT_NODELABEL(fclk), div, 2)
 
-#define BSP_CFG_UCK_SOURCE                                                                         \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_UCK_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(uclk), clk_div, 0)
-#define BSP_CFG_CLKOUT_SOURCE                                                                      \
-	BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_src, RA_CLOCK_SOURCE_DISABLE)
-#define BSP_CFG_CLKOUT_DIV BSP_CLOCK_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(clkout), clk_div, 0)
+#define BSP_CFG_UCK_SOURCE    RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)))
+#define BSP_CFG_UCK_DIV       RA_CGC_CLK_DIV(DT_NODELABEL(uclk), div, 1)
+#define BSP_CFG_CLKOUT_SOURCE RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(clkout)))
+#define BSP_CFG_CLKOUT_DIV    RA_CGC_CLK_DIV(DT_NODELABEL(clkout), div, 1)
 
 #endif /* BSP_CLOCK_CFG_H_ */