Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add initial uRV CPU support. #2098

Merged
merged 4 commits into from
Oct 17, 2024
Merged

Add initial uRV CPU support. #2098

merged 4 commits into from
Oct 17, 2024

Commits on Oct 16, 2024

  1. Configuration menu
    Copy the full SHA
    edb56e7 View commit details
    Browse the repository at this point in the history

Commits on Oct 17, 2024

  1. soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to s…

    …ynchronous memory.
    
    - Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
    - Correctly handle dm bus wishbone adaptation (Added FIFO).
    enjoy-digital committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    9449d25 View commit details
    Browse the repository at this point in the history
  2. soc/cores/cpu/urv: Move ROM init to builder and allow switching betwe…

    …en classical ROM or ROM integrated in CPU.
    enjoy-digital committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    aab8912 View commit details
    Browse the repository at this point in the history
  3. CHANGES.md: Update.

    enjoy-digital committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    5f463db View commit details
    Browse the repository at this point in the history