Add initial uRV CPU support. #2098
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…ynchronous memory. - Replace im bus wishbone adaptation with synchronous memory (for now and initial tests). - Correctly handle dm bus wishbone adaptation (Added FIFO).
…en classical ROM or ROM integrated in CPU.
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uRV is used in White Rabbit project and being able to do some tests with it directly in LiteX could be useful to do some verifications or try to replace it with another CPU in White Rabbit Core (in the aim to reduce resource usage, especially BRAM usage for ROM by moving code execution to SPIFlash (XIP) or HyperRAM).