Verilog: fix for synthesis of continuous assignments #779
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
tautschnig
approved these changes
Oct 18, 2024
tautschnig
reviewed
Oct 18, 2024
src/verilog/verilog_synthesis.cpp
Outdated
| auto lhs_synth = synth_expr(lhs, symbol_statet::CURRENT); | ||
| auto rhs_synth = synth_expr(rhs, symbol_statet::CURRENT); | ||
|
|
||
| equal_exprt equality{lhs_synth, rhs_synth}; |
There was a problem hiding this comment.
We could use std::move here. But likely won’t matter in the grand scheme of things.
The LHS expression of continuous assignments needs to be synthesized.
kroening
force-pushed
the
continuous_assignment1
branch
from
08fc073
to
c9e186e
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The LHS expression of continuous assignments needs to be synthesized.