Verilog: fix for synthesis of continuous assignments

The LHS expression of continuous assignments needs to be synthesized.

regression/verilog/synthesis/continuous_assignment1.desc

@@ -0,0 +1,7 @@
+CORE
+continuous_assignment1.sv
+--module main --bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/synthesis/continuous_assignment1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  wire [31:0] a;
+  assign a[7:0] = 1;
+  assign a[8+:24] = 1;
+
+  assert final (a == 'h101);
+
+endmodule

regression/verilog/synthesis/continuous_assignment2.desc

@@ -0,0 +1,7 @@
+CORE
+continuous_assignment2.sv
+--module main --bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/synthesis/continuous_assignment2.sv

@@ -0,0 +1,15 @@
+module main;
+
+  typedef struct {
+    bit [31:0] f1, f2;
+  } my_struct;
+
+  wire my_struct s;
+
+  assign s.f1 = 1;
+  assign s.f2 = 2;
+
+  assert final (s.f1 == 1);
+  assert final (s.f2 == 2);
+
+endmodule

regression/verilog/synthesis/continuous_assignment3.desc

@@ -0,0 +1,7 @@
+CORE
+continuous_assignment3.sv
+--module main --bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/synthesis/continuous_assignment3.sv

@@ -0,0 +1,11 @@
+module main;
+
+  wire [31:0] array[10];
+
+  assign array[0] = 0;
+  assign array[1] = 1;
+
+  assert final (array[0] == 0);
+  assert final (array[1] == 1);
+
+endmodule

src/verilog/verilog_synthesis.cpp

@@ -2439,8 +2439,6 @@ void verilog_synthesist::synth_force_rec(
   else
     DATA_INVARIANT(false, "unexpected assignment type");
 
-  auto rhs_synth = synth_expr(rhs, symbol_statet::CURRENT);
-
   // If the symbol is marked as a state variable,
   // turn it into a wire now.
   if(symbol.is_state_var)
@@ -2451,7 +2449,10 @@ void verilog_synthesist::synth_force_rec(
     writeable_symbol.is_state_var = false;
   }
 
-  equal_exprt equality{lhs, rhs_synth};
+  auto lhs_synth = synth_expr(lhs, symbol_statet::CURRENT);
+  auto rhs_synth = synth_expr(rhs, symbol_statet::CURRENT);
+
+  equal_exprt equality{lhs_synth, rhs_synth};
   invars.push_back(equality);
 }