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Verilog: fix for synthesis of continuous assignments #1505

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Verilog: fix for synthesis of continuous assignments

Verilog: fix for synthesis of continuous assignments #1505

Triggered via pull request October 18, 2024 13:09
@kroeningkroening
opened #779
continuous_assignment1
Status Success
Total duration 1m 31s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
1m 21s
check-clang-format
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