Tests and Coverpoints for Hints operations

[itsubaidrehman]

Description

This PR includes the Tests and Coverpoints for HINTs operations of RISC-V.

Related Issues

N/A

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

N/A

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports :https://drive.google.com/drive/u/0/folders/1J9YmZio1zSTZgC151xkKcGzSrahKQQ7e

Optional Checklist:

• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[allenjbaum]

I there some particular reason that these individual files can't be combined into (at least) a single per-extension files, e.g. this one would be riscv-test-suite/rv64i_m/hints/src/I_hints-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-d707541a25babf3bb5cea0948c2208afe867c6668cf2c975c38397f070cf9127> and M-extension would be riscv-test-suite/rv64i_m/hints/src/M_hints-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-d707541a25babf3bb5cea0948c2208afe867c6668cf2c975c38397f070cf9127> A riscv-test-suite/rv64i_m/hints/src/xori-01.S (157)

…

On Sun, Jan 19, 2025 at 11:39 PM Ubaid ur Rehman ***@***.***> wrote: Description This PR includes the Tests and Coverpoints for HINTs operations of RISC-V. Related Issues N/A Ratified/Unratified Extensions - Ratified - Unratified List Extensions N/A Reference Model Used - SAIL - Spike - Other - < SPECIFY HERE > Mandatory Checklist: - All tests are compliant with the test-format spec present in this repo ? - Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ? - Ran the new tests on RISCOF in coverage mode <https://riscof.readthedocs.io/en/stable/commands.html#coverage> - Link to Google-Drive folder containing the new coverage reports : https://drive.google.com/drive/u/0/folders/1J9YmZio1zSTZgC151xkKcGzSrahKQQ7e <http://url> Optional Checklist: - Were the tests hand-written/modified ? - Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description - If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above. ------------------------------ You can view, comment on, or merge this pull request online at: #601 Commit Summary - dcb67be <dcb67be> Added hint operations for RV32 - 6419aa6 <6419aa6> Added macros for hints signatures updated - b894929 <b894929> Added coverpoints for hints RV32 - 0863d23 <0863d23> Added tests for hints operations of RV64 - 266731d <266731d> Added coverage for RV64 File Changes (56 files <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files>) - *A* coverage/hints/rv32i.cgf <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-8bf1845f5a1ad61e7d4b48d6442561671479fa5c89ba31c6a841a5ad6ded8105> (397) - *A* coverage/hints/rv64i.cgf <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-2ec849fb5244f17432bbf4fbc5a4f87bc94494ab4e987ea1e843b55d93f27306> (563) - *M* riscv-test-suite/env/test_macros.h <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-86c00a2b5079b1636883cca4bc0c29ef31935d4faabbc72e46926e27004dee77> (41) - *A* riscv-test-suite/rv32i_m/hints/src/add-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-f46896e323ece9a6a0bbb0af7a46f5b41d06ac431cf9695b55757df132ce6e88> (160) - *A* riscv-test-suite/rv32i_m/hints/src/addi-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-e5bd471e19c1943ee261bd4997b408a3d5a4be58a9e16d590abaf3bc3eb147c7> (154) - *A* riscv-test-suite/rv32i_m/hints/src/and-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-751e0152b5abebf60d7d9f5a720ee69f8f1c70dc641a7f3bb9b81e53de334683> (151) - *A* riscv-test-suite/rv32i_m/hints/src/andi-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-14ae8bd9cd96de03fd995a15df519acf7a0899a20587e192760407f9fab96bb7> (152) - *A* riscv-test-suite/rv32i_m/hints/src/auipc-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-9b6c00c27ff4271c0ab1c23a571c7a6ea0b65dac6cfb4ea79f3aa8b6a9843f7d> (169) - *A* riscv-test-suite/rv32i_m/hints/src/fence-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-bbdb728ad47e2cf20a2d6e86e5221f38539c7abd329666f5bde572ad44e64ca9> (65) - *A* riscv-test-suite/rv32i_m/hints/src/lui-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-4385c3749b110861ad0c5921bd62b141c23b0fdb4e38db316dc0339c4dbba6fd> (163) - *A* riscv-test-suite/rv32i_m/hints/src/or-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-4902cc4bbd05e566dc28a692e78aec31c868d0c5a71c671873917737c0a9e565> (157) - *A* riscv-test-suite/rv32i_m/hints/src/ori-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-a5447d9a90e979d0c799897ec8d7391969bcbf58268207a700f8e092c670a1f8> (167) - *A* riscv-test-suite/rv32i_m/hints/src/sll-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-6d2fb8921b32aac9d30fc0d2644041cd6b8650bf531799b27b4c1a0a2757f3c8> (157) - *A* riscv-test-suite/rv32i_m/hints/src/slli-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-e9bd1e353fbba63844b3cc3970312e13fcc8d89d07fafd795a4d24d676c5cb50> (176) - *A* riscv-test-suite/rv32i_m/hints/src/slt-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-9853e19ac6b5f54bee1366e4503abc6ba72b3afb61e9346d9762fd4465c9e253> (153) - *A* riscv-test-suite/rv32i_m/hints/src/slti-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-c22dd90e7b702f8a4f23a337fe7dc404b74af93b7550d3528d19a4cbc741e1be> (175) - *A* riscv-test-suite/rv32i_m/hints/src/sltiu-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-5e55b72da17ad00f6fdc1b785cc7ce78bda566617ac1290f6218cbbfc1265b32> (166) - *A* riscv-test-suite/rv32i_m/hints/src/sltu-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-54ae19c0620efa2a178d05cb6f74a0d36e0bf410face1bf60740b18d5b68d821> (164) - *A* riscv-test-suite/rv32i_m/hints/src/sra-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-02c5f90455df76bf646dc82fefaf7cd82b7179470f1828389b39d0c5baad56f9> (156) - *A* riscv-test-suite/rv32i_m/hints/src/srai-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-7f8badc0136843f54edad825a4d8dededa5df74462037d52fed3781147920569> (156) - *A* riscv-test-suite/rv32i_m/hints/src/srl-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-c3806c6711bbbf16b14bd0f192c7fadd1e4f084f48e5ba4072d5c465858286b1> (160) - *A* riscv-test-suite/rv32i_m/hints/src/srli-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-283f13c231baeaa1522e044c5a1666d002aab45eb01f3e6c31de03381cf609b0> (175) - *A* riscv-test-suite/rv32i_m/hints/src/sub-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-0e81b4371121aba66ea4c0388dfd2a7da7b0d4c0d5a8b1e8dfd750fbd54526b3> (160) - *A* riscv-test-suite/rv32i_m/hints/src/xor-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-9968707edceafe681038698c3b9db963d1ea4894a929d3dfc4425f84ea2fcb75> (161) - *A* riscv-test-suite/rv32i_m/hints/src/xori-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-06a742932e2acdf5ab6a7b620b6750fd7adc90f6839b9f1467a68d570e2ce4a2> (156) - *A* riscv-test-suite/rv64i_m/hints/src/add-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-0ea470f9efc6e40a0bc9803e2182008b8078de8f26d5765b7362daa2f0cb06e7> (170) - *A* riscv-test-suite/rv64i_m/hints/src/addi-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-db30d39c3d74e044e7f27533a484e0fe30a904b464dc3f511b7719c8bfed6bc6> (158) - *A* riscv-test-suite/rv64i_m/hints/src/addiw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-0f2a6f15a4799d9cdfeaecf6d9555472c8eb1673a6cafbde58ff054e09ca8142> (155) - *A* riscv-test-suite/rv64i_m/hints/src/addw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-cb2ba49486044053758261b54cbce66b92775f344e4159c8f6f551a8916b7005> (158) - *A* riscv-test-suite/rv64i_m/hints/src/and-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-ae6e81c082e74b4ed954e4a6a03258b4de503f5e7da40a1e5ea0d0d67e0b5ae3> (174) - *A* riscv-test-suite/rv64i_m/hints/src/andi-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-ec8042962e4ea490cbef682584c2546961024d6e25e0e55709961146d3eb7b15> (158) - *A* riscv-test-suite/rv64i_m/hints/src/auipc-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-44d75f8f30be83a4033d55b31e4ea61d6aed15a8712806346a307237aebf3a61> (158) - *A* riscv-test-suite/rv64i_m/hints/src/fence-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-8df4d3c86cd6202170cdfc3198a5407d24b4559cf9b6b9c9e72bfbf58f9cb7ba> (69) - *A* riscv-test-suite/rv64i_m/hints/src/lui-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-6847fc84934ac21003c0fb4fbe09ada6cbcb08be1029069802bc1bde19a8afb3> (157) - *A* riscv-test-suite/rv64i_m/hints/src/or-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-8bd7f49a246b013d29ffed752e681a0335077664af5e8132748ebbbf12fb9037> (153) - *A* riscv-test-suite/rv64i_m/hints/src/ori-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-6efb126a75df6834f85fdc7d381bc984be67a2297f2803a07359807c86a913f5> (156) - *A* riscv-test-suite/rv64i_m/hints/src/sll-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-51afdac3d43f7923464240125a5cd3beab8c17d3ee69a3b715baf5828b423cfe> (158) - *A* riscv-test-suite/rv64i_m/hints/src/slli-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-8276689a161cef3368c78d20d2cfaec702aa0b083606fbedbc06cfad62e92398> (151) - *A* riscv-test-suite/rv64i_m/hints/src/slliw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-82272657344af534cb2240bd9cd1b6d200a9126c54de001552ef99045703cf77> (156) - *A* riscv-test-suite/rv64i_m/hints/src/sllw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-8c088761f859e543f13af941aa5b6154657bcdec1639d8d0d9977c301ba39a6f> (157) - *A* riscv-test-suite/rv64i_m/hints/src/slt-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-b29655e932b0f6f1befec6ab10b1bb45f8ab5a47b593f66747e913075bb18a49> (157) - *A* riscv-test-suite/rv64i_m/hints/src/slti-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-68c031e2a0c4fcb6f66c5b213ac2f1582322415d5e8cd2e62a0cdc50f043bf90> (157) - *A* riscv-test-suite/rv64i_m/hints/src/sltiu-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-d96bf582ae3fbc80da8de303030b168148f1a44bd127a123ea43929905a17cbe> (157) - *A* riscv-test-suite/rv64i_m/hints/src/sltu-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-c02b07a19c8ad6b40338597dbbf989787b654dbf1b2fb2ad543dcd8fd01aa32c> (160) - *A* riscv-test-suite/rv64i_m/hints/src/sra-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-86c6cf1bd21404120264598c21a8fc7ca3219b94de9ee97d934797fc6461e889> (158) - *A* riscv-test-suite/rv64i_m/hints/src/srai-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-dfe3b11b6e4fb544e050d5b3b8448729fac7633b9e41961dc020a96abaa78093> (157) - *A* riscv-test-suite/rv64i_m/hints/src/sraiw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-1e4c00cf4048eb0425c2d04f8092475a491d23e07320daa3095b9e3f42c90aa1> (159) - *A* riscv-test-suite/rv64i_m/hints/src/sraw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-7305335ff5e987852d637cee25711f70be6a17d187c13df251f3ff98f72d1a48> (154) - *A* riscv-test-suite/rv64i_m/hints/src/srl-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-f5a35d94b341529803fde53bf6ba68821e5ad53454911bc1383ebf27c3c23a24> (155) - *A* riscv-test-suite/rv64i_m/hints/src/srli-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-9547f3ad99153d0c6f1555ad088dd63cad5b239763f576445cb36db105146c16> (156) - *A* riscv-test-suite/rv64i_m/hints/src/srliw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-cc77ae3f6b50bafc599440ba462233be17b004bdd467efe0d19037d4705ea71f> (157) - *A* riscv-test-suite/rv64i_m/hints/src/srlw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-dbad409a58ddf19be5d75fc30c1cea70b07b7c21d6165016f40ab8fe21bf5316> (157) - *A* riscv-test-suite/rv64i_m/hints/src/sub-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-4d415a38b64d899ddaf6528228da4ee6d8a79e4f0941ff930e1f4888ea70c350> (156) - *A* riscv-test-suite/rv64i_m/hints/src/subw-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-356c9f04aff32eba3c59f11514bd970ac7ba0e02a634dae47d0b5d1b38baccf4> (158) - *A* riscv-test-suite/rv64i_m/hints/src/xor-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-ada384408ef7dabcd7b542e7a2d10c0eaf41af09a045c91d4d320bdff00d1bc5> (156) - *A* riscv-test-suite/rv64i_m/hints/src/xori-01.S <https://github.com/riscv-non-isa/riscv-arch-test/pull/601/files#diff-d707541a25babf3bb5cea0948c2208afe867c6668cf2c975c38397f070cf9127> (157) Patch Links: - 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[itsubaidrehman]

@allenjbaum I have kept the files separate for each instruction for ease of maintenance. This approach ensures that when new hints are added to any extension, a new file can be created to develop tests for that instruction without requiring modifications to existing files.