Adding tests for covering registers as described in issue number 306

[MuhammadHammad001]

Description

This PR contains the div-01.S files changed for the coverpoints mentioned in issue#306. I have generated the tests for the following coverpoints using the solution proposed in PR#79. The tests are generated the same way, the only changes were made in dataset.cgf for the addition of coverpoints and also in the generator.py of riscv-ctg. Please refer to the above mentioned PR#79 to see which changes were made in generator.py
Note: Please follow the following format for the hardcode value registers for proper generation of tests.

     'rs1 == rd != rs2; rd != "x0"': 0
     'rs1 == rd != rs2; rd == "x0"': 0
     'rs1 == "x0" != rd': 0
     'rd == "x0" != rs1': 0

Related Issues

issue#306

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

RV32IM
RV64IM

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports (See this for more info): PR#385
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : PR#79.
• Were the tests hand-written/modified ? -- div-01.S was modified.
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[allenjbaum]

We now see example of rs1, rs2, and rd all selecting X0

[allenjbaum]

This needs the changelog entry to be updated, and then it's good to go

[allenjbaum]

I should have asked you to pull form the latest changelog before pushing the change; there were several merges going on at the same time...

[allenjbaum]

Well, it looks likere are 2 v3.7.2, let's see what hap[ens