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Refactor: Improve RISC-V interrupt and CSR handling consistency
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@Ali-Faraz-10xe
Ali-Faraz-10xe committed Dec 9, 2024
1 parent 08d836e commit 9181a36
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60 changes: 37 additions & 23 deletions coverage/header_file.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,9 @@ common:
MSTATUS_UXL: 0x0000000300000000
MSTATUS_SXL: 0x0000000C00000000
MSTATUS64_SD: 0x8000000000000000
MSTATUS_MPP_M: 0x1800
MSTATUS_MPP_S: 0x800
MSTATUS_MPP_U: 0x000
SSTATUS_UIE: 0x00000001
SSTATUS_SIE: 0x00000002
SSTATUS_UPIE: 0x00000010
Expand Down Expand Up @@ -81,15 +84,6 @@ common:
PMP_TOR: 0x08
PMP_NA4: 0x10
PMP_NAPOT: 0x18
IRQ_S_SOFT: 1
IRQ_H_SOFT: 2
IRQ_M_SOFT: 3
IRQ_S_TIMER: 5
IRQ_H_TIMER: 6
IRQ_M_TIMER: 7
IRQ_S_EXT: 9
IRQ_H_EXT: 10
IRQ_M_EXT: 11
IRQ_COP: 12
IRQ_HOST: 13
DEFAULT_RSTVEC: 0x00001000
Expand Down Expand Up @@ -863,6 +857,16 @@ common:
CAUSE_FETCH_PAGE_FAULT: 0xc
CAUSE_LOAD_PAGE_FAULT: 0xd
CAUSE_STORE_PAGE_FAULT: 0xf
CAUSE_S_SOFT_INTR: (0x1)
CAUSE_H_SOFT_INTR: (0x2)
CAUSE_M_SOFT_INTR: (0x3)
CAUSE_S_TIMER_INTR: (0x5)
CAUSE_H_TIMER_INTR: (0x6)
CAUSE_M_TIMER_INTR: (0x7)
CAUSE_S_EXT_INTR: (0x9)
CAUSE_H_EXT_INTR: (0x10)
CAUSE_M_EXT_INTR: (0x11)
INTERRUPT_MASK: (0XF)
CSR_MENTROPY: 0xF15
CSR_MNOISE: 0x7A9
DCSR_XDEBUGVER: (3U<<30)
Expand Down Expand Up @@ -891,17 +895,26 @@ common:
MCONTROL_EXECUTE: (1<<2)
MCONTROL_STORE: (1<<1)
MCONTROL_LOAD: (1<<0)
MIP_SSIP: (1 << IRQ_S_SOFT)
MIP_HSIP: (1 << IRQ_H_SOFT)
MIP_MSIP: (1 << IRQ_M_SOFT)
MIP_STIP: (1 << IRQ_S_TIMER)
MIP_HTIP: (1 << IRQ_H_TIMER)
MIP_MTIP: (1 << IRQ_M_TIMER)
MIP_SEIP: (1 << IRQ_S_EXT)
MIP_HEIP: (1 << IRQ_H_EXT)
MIP_MEIP: (1 << IRQ_M_EXT)
MIP_SSIP: (1<<1)

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@allenjbaum

allenjbaum Dec 23, 2024

Collaborator

To avoid problems in the future, I would remove the constants and replace them with the variables defined above, e.g. 1<<6 should be replace with 1<< CAUSE_H_EXT_INTR

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@allenjbaum

allenjbaum Dec 23, 2024

Collaborator

Actually, it should be replaced with
IRQ_H_EXT in the CAUSE definitions, and
1<< IRQ_H_EXT in the MIP and MIE definition
MIP_HSIP: (1<<2)
MIP_MSIP: (1<<3)
MIP_STIP: (1<<5)
MIP_HTIP: (1<<6)
MIP_MTIP: (1<<7)
MIP_SEIP: (1<<9)
MIP_HEIP: (1<<10)
MIP_MEIP: (1<<11)
MIE_SSIE: (1<<1)
MIE_HSIE: (1<<2)
MIE_MSIE: (1<<3)
MIE_STIE: (1<<5)
MIE_HTIE: (1<<6)
MIE_MTIE: (1<<7)
MIE_SEIE: (1<<9)
MIE_HEIE: (1<<10)
MIE_MEIE: (1<<11)
RISCV_PGSIZE: (1 << RISCV_PGSHIFT)

PMP_MACROS:
PMPCFG_BIT_SET: 1
PMPCFG_BIT_NOT_SET: 0
Expand Down Expand Up @@ -933,8 +946,9 @@ PMP_helper_Coverpoints:
NA4_REGION_ADDRESS_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
NA4_PRIORITY_REGION_MATCH: (rs1_val + imm_val == (pmpaddr3 << 2))
NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))

Interrupt_Macros:
MSIP_BASE: 0x02000000
MTIMECMP_BASE: 0x02004000
MTIME_BASE: 0x0200bff8
RVMODEL_MSIP_BASE: 0x02000000
RVMODEL_MTIMECMP_BASE: 0x02004000
RVMODEL_MTIME_BASE: 0x0200bff8

56 changes: 28 additions & 28 deletions coverage/rv32_m_interrupts.cgf
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62 changes: 31 additions & 31 deletions coverage/rv64_m_interrupts.cgf
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33 changes: 23 additions & 10 deletions riscof-plugins/rv32/sail_cSim/env/model_test.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,10 @@
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H

#define RVMODEL_MSIP_BASE 0x02000000
#define RVMODEL_MTIME_BASE 0x0200bff8
#define RVMODEL_MTIMECMP_BASE 0x02004000

#define RVMODEL_DATA_SECTION \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
Expand Down Expand Up @@ -46,21 +50,30 @@ RVMODEL_DATA_SECTION ;\
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#define RVMODEL_SET_MSW_INT ;\
li t1, 1 ;\
li t2, 0x2000000 ;\
SREG t1, 0(t2) ;\
LI( T1, 1) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MSW_INT ;\
li t0, 0x2000000 ;\
SREG x0, 0(t0) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG x0, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
li t0, 0x02004000 ;\
li t2, -1 ;\
SREG t2, 0(t0) ;\

#define RVMODEL_SET_MTIMER_INT ;\
LI( T1, 0xFFFFF) ;\
LI( T2, RVMODEL_MTIME_BASE) ;\
SREG T1, 0(T2) ;\
nop ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
LI( T1, -1) ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MEXT_INT

Expand Down
1 change: 0 additions & 1 deletion riscof-plugins/rv32/sail_cSim/riscof_sail_cSim.py
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Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,6 @@ def runTests(self, testList, cgf_file=None, header_file= None):
coverage_cmd = 'riscv_isac --verbose info coverage -d \
-t {0}.log --parser-name c_sail -o coverage.rpt \
--sig-label begin_signature end_signature \
--test-label rvtest_code_begin rvtest_code_end \
-e ref.elf -c {1} -x{2} {3} {4} {5};'.format(\
test_name, ' -c '.join(cgf_file), self.xlen, cov_str, header_file_flag, cgf_mac)
else:
Expand Down
34 changes: 24 additions & 10 deletions riscof-plugins/rv32/spike_simple/env/model_test.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,10 @@
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H

#define RVMODEL_MSIP_BASE 0x02000000
#define RVMODEL_MTIME_BASE 0x0200bff8
#define RVMODEL_MTIMECMP_BASE 0x02004000

#if XLEN == 64
#define ALIGNMENT 3
#else
Expand Down Expand Up @@ -49,21 +54,30 @@ li x1, 1 ;\
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#define RVMODEL_SET_MSW_INT ;\
li t1, 1 ;\
li t2, 0x2000000 ;\
SREG t1, 0(t2) ;\
LI( T1, 1) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MSW_INT ;\
li t0, 0x2000000 ;\
SREG x0, 0(t0) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG x0, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
li t0, 0x02004000 ;\
li t2, -1 ;\
SREG t2, 0(t0) ;\

#define RVMODEL_SET_MTIMER_INT ;\
LI( T1, 0xFFFFF) ;\
LI( T2, RVMODEL_MTIME_BASE) ;\
SREG T1, 0(T2) ;\
nop ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
LI( T1, -1) ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MEXT_INT

Expand Down
33 changes: 23 additions & 10 deletions riscof-plugins/rv64/sail_cSim/env/model_test.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,10 @@
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H

#define RVMODEL_MSIP_BASE 0x02000000
#define RVMODEL_MTIME_BASE 0x0200bff8
#define RVMODEL_MTIMECMP_BASE 0x02004000

#define RVMODEL_DATA_SECTION \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
Expand Down Expand Up @@ -44,21 +48,30 @@ li x1, 1 ;\
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#define RVMODEL_SET_MSW_INT ;\
li t1, 1 ;\
li t2, 0x2000000 ;\
SREG t1, 0(t2) ;\
LI( T1, 1) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MSW_INT ;\
li t0, 0x2000000 ;\
SREG x0, 0(t0) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG x0, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
li t0, 0x02004000 ;\
li t2, -1 ;\
SREG t2, 0(t0) ;\

#define RVMODEL_SET_MTIMER_INT ;\
LI( T1, 0xFFFFF) ;\
LI( T2, RVMODEL_MTIME_BASE) ;\
SREG T1, 0(T2) ;\
nop ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
LI( T1, -1) ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MEXT_INT

Expand Down
1 change: 0 additions & 1 deletion riscof-plugins/rv64/sail_cSim/riscof_sail_cSim.py
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Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,6 @@ def runTests(self, testList, cgf_file=None, header_file= None):
coverage_cmd = 'riscv_isac --verbose info coverage -d \
-t {0}.log --parser-name c_sail -o coverage.rpt \
--sig-label begin_signature end_signature \
--test-label rvtest_code_begin rvtest_code_end \
-e ref.elf -c {1} -x{2} {3} {4} {5};'.format(\
test_name, ' -c '.join(cgf_file), self.xlen, cov_str, header_file_flag, cgf_mac)
else:
Expand Down
34 changes: 24 additions & 10 deletions riscof-plugins/rv64/spike_simple/env/model_test.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,10 @@
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H

#define RVMODEL_MSIP_BASE 0x02000000
#define RVMODEL_MTIME_BASE 0x0200bff8
#define RVMODEL_MTIMECMP_BASE 0x02004000

#define RVMODEL_DATA_SECTION \
.pushsection .tohost,"aw",@progbits; \
.align 8; .global tohost; tohost: .dword 0; \
Expand Down Expand Up @@ -44,21 +49,30 @@ li x1, 1 ;\
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)

#define RVMODEL_SET_MSW_INT ;\
li t1, 1 ;\
li t2, 0x2000000 ;\
SREG t1, 0(t2) ;\
LI( T1, 1) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MSW_INT ;\
li t0, 0x2000000 ;\
SREG x0, 0(t0) ;\
LI( T2, RVMODEL_MSIP_BASE) ;\
SREG x0, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
li t0, 0x02004000 ;\
li t2, -1 ;\
SREG t2, 0(t0) ;\

#define RVMODEL_SET_MTIMER_INT ;\
LI( T1, 0xFFFFF) ;\
LI( T2, RVMODEL_MTIME_BASE) ;\
SREG T1, 0(T2) ;\
nop ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MTIMER_INT ;\
LI( T1, -1) ;\
LI( T2, RVMODEL_MTIMECMP_BASE) ;\
SREG T1, 0(T2) ;\
nop ;

#define RVMODEL_CLR_MEXT_INT

Expand Down
54 changes: 34 additions & 20 deletions riscv-test-suite/env/arch_test.h
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Original file line number Diff line number Diff line change
Expand Up @@ -985,10 +985,13 @@ init_\__MODE__\()scratch:
csrrw T3, CSR_XSCRATCH, T1 // swap xscratch with save area ptr (will be used by handler)
SREG T3, xscr_save_off(T1) // save old mscratch in xscratch_save
//----------------------------------------------------------------------
#ifdef RVMODEL_MTIMECMP_BASE
init_mtimecmp:
li t0, 0x2004000
li t2, -1
SREG t2, 0(t0)
LI( T2, -1)
LI( T4, RVMODEL_MTIMECMP_BASE)
SREG T2, 0(T4)
nop
#endif
//----------------------------------------------------------------------
init_\__MODE__\()edeleg:

Expand Down Expand Up @@ -1510,24 +1513,35 @@ resto_\__MODE__\()rtn: // restore and return
/**** clears the int and saves int-specific CSRS****/
/***************************************************/
common_\__MODE__\()int_handler: // T1 has sig ptr, T5 has mcause, sp has save area
li T3, 1
//**FIXME** - make sure this is kept up-to-date with fast int extension and others
LI( T3, 1)
andi T2, T5, INT_CAUSE_MSK // clr INT & unarched arched bits (**NOTE expand if future extns use them)
sll T3, T3, T2 // create mask 1<<xcause **NOTE**: that MSB is ignored in shift amt
csrrc T4, CSR_XSTATUS, T3 // read then attempt to clear mstatus??
srli T4, T4, 3 // Move MIE to LSB
andi T4, T4, 1 // Mask MIE
sv_\__MODE__\()status: // note: clear has no effect on MxSTATUS
SREG T4, 2*REGWIDTH(T1) // save 3rd sig value, (xstatus)
csrrc T4, CSR_XIE, T3 // read, then attempt to clear int enable bit??
sv_\__MODE__\()ie: // note: clear has no effect on MxIE
SREG T4, 3*REGWIDTH(T1) // save 4th sig value, (xie)
csrrc T4, CSR_XIP, T3 // read, then attempt to clear int pend bit??
sv_\__MODE__\()ip: // note: clear has no effect on MxIP
SREG T4, 4*REGWIDTH(T1) // save 5th sig value, (xip)
sll T3, T3, T2 // create mask 1<<xcause **NOTE**: that MSB is ignored in shift amt
csrrc T2, CSR_MIDELEG, x0 // read machine interrupt delegation
nop // if mideleg is not used and trap occur
and T2, T2, T3 // mask caused interrupt delegation bit
srl T2, T2, T3 // Move interrupt delegation to LSB
LI (T4, 1)
beq T2, T4, sv_\__MODE__\()status // if interrupt delegation bit is set then read and store SIE and SPIE in signature
LI( T2, 3) // if interrupt delegation bit is not set then read and store MIE and MPIE in signature
sv_\__MODE__\()status: // note: clear has no effect on XxSTATUS
csrrc T4, CSR_XSTATUS, x0 // read xstatus
srl T4, T4, T2 // move xIE to LSB
andi T4, T4, 0b10001 // mask xIE and xPIE
SREG T4, 2*REGWIDTH(T1) // save 3rd sig value, (xstatus.XIE and xstatus.XPIE)
nop
sv_\__MODE__\()ie: // note: clear has no effect on XxIE
csrrc T4, CSR_XIE, x0 // read then attempt to clear int enable bit??
and T4, T4, T3 // mask XxIE
SREG T4, 3*REGWIDTH(T1) // save 4th sig value, (XxIE)
nop
sv_\__MODE__\()ip: // note: clear has no effect on XxIP
csrrc T4, CSR_XIP, x0 // read, then attempt to clear int pend bit??
and T4, T4, T3 // mask XxIP
SREG T4, 4*REGWIDTH(T1) // save 5th sig value, (XxIP)
nop


li T2, 0 // index of interrupt dispatch table base
LI( T2, 0) // index of interrupt dispatch table base

/**************************************************************/
/**** spcl int/excp dispatcher. T5 has mcause, T2 ****/
Expand Down Expand Up @@ -2035,7 +2049,7 @@ CANARY
.endm

// Tests allocate normal signature space here, then define
// the mtrap_sigptr: label to separate normal and trap
// the mtrap_sigptr: label to separate normal and t
// signature space, then allocate trap signature space

/********************* REQUIRED FOR NEW TESTS *************************/
Expand Down
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