Merge pull request #454 from wychlw/main

Fix: RVTEST_CASE missing ISA
riscv-non-isa · Apr 17, 2024 · 59ae6e7 · 59ae6e7
2 parents c443e5c + 8e333bc
commit 59ae6e7
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Showing 12 changed files with 14 additions and 11 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # CHANGELOG
 
+## [3.8.14] - 2024-04-16
+Add missing `Zfh` ISA in RVTEST_CASE for `Zfh` fdiv related tests
+
 ## [3.8.13] - 2024-04-13
 - Fixed missing `F` and `Zfh` ISA identifiers in `Zfh/flh-align-01` RVTEST_CASE macro.
 

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b1-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b1)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b1)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b2-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b2-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b2)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b2)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b20-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b20-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b20)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b20)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b21-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b21-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b21)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b21)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b3-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b3-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b3)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b3)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b4-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b4-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b4)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b4)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b5-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b5-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b5)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b5)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b6-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b6-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b6)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b6)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b7-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b7-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b7)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b7)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b8-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b8-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b8)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b8)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b9-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b9-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b9)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fdiv_b9)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)