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adding test of adding read-only csr mconfigptr
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mconfigptr is used by the unified discovery task group https://github.com/riscv/configuration-structure

requires riscv/sail-riscv#293 to pass (sail had not implemented mconfigptr)
requires updated encoding.h
passes sail and spike
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dansmathers authored Aug 16, 2023
1 parent de395c5 commit 3c0288c
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77 changes: 77 additions & 0 deletions riscv-test-suite/rv32i_m/privilege/src/mconfigptr.S
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// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the mconfigptr CSR read access.
//

#include "model_test.h"
#include "arch_test.h"

RVTEST_ISA("RV32I_Zicsr")

# Test code region
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

RVTEST_SIGBASE( a1,signature_a1_m) // a1 will point to signature_a1_m label in the signature region - m-mode

#ifdef TEST_CASE_1
RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",mconfigptr)

# ---------------------------------------------------------------------------------------------
csrr t1, CSR_MCONFIGPTR

LI( t0,0x12345678)
csrw CSR_MCONFIGPTR, t0

sub t0, t0, t1
csrr t0, CSR_MCONFIGPTR
RVTEST_SIGUPD( a1,t0)

RVMODEL_IO_WRITE_STR(x30, "# Test part A - test MCONFIGPTR\n");

RVMODEL_IO_WRITE_STR(x30, "# Test End\n")

#endif

# ---------------------------------------------------------------------------------------------
# HALT

RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
# Input data section.
.data
.align 4
RVTEST_DATA_END

# Output data section.
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
signature_a1_m:
.fill 32*(XLEN/32),4,0xdeadbeef

sig_begin_canary:
CANARY;

test_A_res:
.fill 2, 4, 0xdeadbeef

mtrap_sigptr:
.fill 4, 4, 0xdeadbeef

#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32), 4, 0xdeadbeef
#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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