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Sim model synth properties (#1598)
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* Initial port property, sim models update

* Initial port property, sim models update

* netlist edit fix, power tool fix
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@alaindargelas
alaindargelas authored Mar 19, 2024
1 parent 588565d commit a8efcd6
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion yosys_verific_rs
Submodule yosys_verific_rs updated 4 files
+1 −1 CMakeLists.txt
+34 −80 design_edit/src/rs_design_edit.cc
+0 −2 design_edit/src/rs_design_edit.h
+320 −113 pow_extract/src/rs_pow_extract.cc

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