Skip to content
View alaindargelas's full-sized avatar

Organizations

@alainmarcel

Block or report alaindargelas

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. synlig synlig Public

    Forked from chipsalliance/synlig

    SystemVerilog support for Yosys

    Verilog 1 1

  2. vtr-verilog-to-routing vtr-verilog-to-routing Public

    Forked from verilog-to-routing/vtr-verilog-to-routing

    Verilog to Routing -- Open Source CAD Flow for FPGA Research

    C++

  3. OpenFPGA OpenFPGA Public

    Forked from lnis-uofu/OpenFPGA

    An Open-source FPGA IP Generator

    Verilog

  4. OpenSTA OpenSTA Public

    Forked from Silimate/OpenSTA

    OpenSTA Silimate fork

    C++

  5. yosys yosys Public

    Forked from Silimate/yosys

    Yosys Open SYnthesis Suite

    C++