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Bitstream sim (#1544)
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* Bitstream sim

* Design edit init

* Build number
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alaindargelas authored Feb 28, 2024
1 parent 6ea94e5 commit 95bb544
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2 changes: 1 addition & 1 deletion CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,7 @@ add_subdirectory(IP_Catalog)
# Raptor version
set(VERSION_MAJOR 1)
set(VERSION_MINOR 0)
set(VERSION_PATCH 1)
set(VERSION_PATCH 2)

execute_process(COMMAND git config --global --add safe.directory ${CMAKE_CURRENT_SOURCE_DIR}
COMMAND git rev-parse --short HEAD
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2 changes: 1 addition & 1 deletion FOEDAG_rs
Submodule FOEDAG_rs updated 1 files
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2 changes: 1 addition & 1 deletion yosys_verific_rs
Submodule yosys_verific_rs updated 33 files
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+105 −0 design_edit/Makefile
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+32 −0 design_edit/Tests/non_primitive_design/rtl/and2.v
+15 −0 design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.eblif
+62 −0 design_edit/Tests/non_primitive_design/synthesis/and2_post_synth.v
+19 −0 design_edit/Tests/primitive_example_design_1/primitive_example_design_1.ys
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+19 −0 design_edit/Tests/primitive_example_design_3/primitive_example_design_3.ys
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+134 −0 design_edit/Tests/primitive_example_design_4/synthesis/primitive_example_design_4_post_synth.v
+19 −0 design_edit/Tests/primitive_example_design_5/primitive_example_design_5.ys
+37 −0 design_edit/Tests/primitive_example_design_5/rtl/primitive_example_design_5.v
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+190 −0 design_edit/Tests/primitive_example_design_5/synthesis/primitive_example_design_5_post_synth.v
+19 −0 design_edit/Tests/primitive_example_design_6/primitive_example_design_6.ys
+27 −0 design_edit/Tests/primitive_example_design_6/rtl/primitive_example_design_6.v
+17 −0 design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.eblif
+106 −0 design_edit/Tests/primitive_example_design_6/synthesis/primitive_example_design_6_post_synth.v
+24,640 −0 design_edit/include/json.hpp
+17 −0 design_edit/run_tests.sh
+570 −0 design_edit/src/rs_design_edit.cc

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