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RAM mapping fixes (#1523)
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@alaindargelas
alaindargelas authored Feb 16, 2024
1 parent 8c859dc commit 9380a78
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2 changes: 1 addition & 1 deletion Backend
Submodule Backend updated 2 files
+1 −1 OpenFPGA
+1 −1 Raptor_Tools
2 changes: 1 addition & 1 deletion Raptor_Tools
Submodule Raptor_Tools updated 2 files
+231 −25 gatelevel_readers/reconstruct_verilog/src/reconstruct_ram18kx2.h
+1 −145 gatelevel_readers/reconstruct_verilog/tests/RAM/golden/TDP_RAM18KX2_primitive_inst_post_synth_golden.eblif
2 changes: 1 addition & 1 deletion yosys_verific_rs
Submodule yosys_verific_rs updated 3 files
+5 −2 .github/workflows/version.yml
+1 −1 CMakeLists.txt
+1 −1 yosys-rs-plugin

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