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Fix BRAM init bug (#1533)
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@alaindargelas
alaindargelas authored Feb 23, 2024
1 parent 75838ca commit 3c24d5b
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Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion Backend
Submodule Backend updated 5 files
+5 −9 .github/dependabot.yml
+4 −1 .github/workflows/labeler.yml
+20 −3 CMakeLists.txt
+1 −1 OpenFPGA
+1 −1 Raptor_Tools
2 changes: 1 addition & 1 deletion Raptor_Tools
Submodule Raptor_Tools updated 10 files
+17 −7 gatelevel_readers/reconstruct_verilog/src/reconstruct_ram18kx2.h
+11 −13 gatelevel_readers/reconstruct_verilog/src/reconstruct_ram36k.h
+20 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM18Kx2_MEM_CHECK/Makefile
+186 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM18Kx2_MEM_CHECK/main.cpp
+48 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM18Kx2_MEM_CHECK/new_sim.v
+10 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM18Kx2_MEM_CHECK/run.sh
+20 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM36K_MEM_CHECK/Makefile
+151 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM36K_MEM_CHECK/main.cpp
+51 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM36K_MEM_CHECK/new_sim.v
+10 −0 gatelevel_readers/reconstruct_verilog/tests/RAM/RAM36K_MEM_CHECK/run.sh

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