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@riscv-non-isa RISC-V Non-ISA Specifications

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    35 repositories

    • riscv-ras-eri

      Public
      The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…
      TeX
      •
      Creative Commons Attribution 4.0 International
      •5•9•0•0•Updated Jan 25, 2025Jan 25, 2025

    • riscv-sbi-doc

      Public
      Documentation for the RISC-V Supervisor Binary Interface
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •94•372•14•5•Updated Jan 24, 2025Jan 24, 2025

    • riscv-security-model

      Public
      RISC-V Security Model
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •15•29•4•1•Updated Jan 23, 2025Jan 23, 2025

    • riscv-elf-psabi-doc

      Public
      A RISC-V ELF psABI Document
      Python
      •
      Creative Commons Attribution 4.0 International
      •165•734•56•27•Updated Jan 23, 2025Jan 23, 2025

    • riscv-toolchain-conventions

      Public
      Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •39•147•15•9•Updated Jan 21, 2025Jan 21, 2025

    • riscv-semihosting

      Public
      Makefile
      •
      Creative Commons Attribution Share Alike 4.0 International
      •9•28•1•0•Updated Jan 21, 2025Jan 21, 2025

    • server-soc

      Public
      The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •8•22•2•0•Updated Jan 20, 2025Jan 20, 2025

    • riscv-arch-test

      Public
      Assembly
      •
      Apache License 2.0
      •214•533•48•38•Updated Jan 20, 2025Jan 20, 2025

    • riscv-server-platform

      Public
      The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.
      platformserverosstandardsinteroperabilityuefihypervisorsacpirisc-vbrs-i
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •5•10•9•3•Updated Jan 20, 2025Jan 20, 2025

    • riscv-external-debug-security

      Public
      The RISC-V External Debug Security Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•19•0•0•Updated Jan 20, 2025Jan 20, 2025

    • riscv-rpmi

      Public
      RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control
      platformmessagingstandardsinteroperabilityriscvrpmiriscv-rpmi
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •9•9•3•0•Updated Jan 16, 2025Jan 16, 2025

    • riscv-c-api-doc

      Public
      Documentation of the RISC-V C API
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •42•74•17•10•Updated Jan 14, 2025Jan 14, 2025

    • riscv-brs

      Public
      The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.
      platformfirmwarestandardsinteroperabilityuefidevicetreeacpismbiosrisc-vbrs-i
      TeX
      •
      Creative Commons Attribution 4.0 International
      •15•45•23•1•Updated Jan 13, 2025Jan 13, 2025

    • riscv-acpi-rimt

      Public
      RISC-V ACPI I/O Mapping Table Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•2•0•1•Updated Jan 13, 2025Jan 13, 2025

    • iopmp-spec

      Public
      This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •6•20•0•2•Updated Jan 6, 2025Jan 6, 2025

    • riscv-ap-tee

      Public
      This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
      securityvirtualizationteetsmconfidential-computingconfidential-vmh-extensionsmmttsupervisor-domains
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •22•52•24•0•Updated Jan 3, 2025Jan 3, 2025

    • tg-nexus-trace

      Public
      RISC-V Nexus Trace TG documentation and reference code
      nexustracerisc-v
      C
      •
      Creative Commons Attribution 4.0 International
      •36•48•5•1•Updated Jan 3, 2025Jan 3, 2025

    • riscv-iommu

      Public
      RISC-V IOMMU Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •18•102•1•3•Updated Dec 25, 2024Dec 25, 2024

    • riscv-trace-spec

      Public
      RISC-V Processor Trace Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •49•168•28•14•Updated Dec 23, 2024Dec 23, 2024

    • riscv-asm-manual

      Public
      RISC-V Assembly Programmer's Manual
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •242•1.5k•6•8•Updated Dec 20, 2024Dec 20, 2024

    • riscv-cbqri

      Public
      This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •8•4•0•1•Updated Dec 18, 2024Dec 18, 2024

    • server-soc-ts

      Public
      Test suite for Server SoC
      Apache License 2.0
      •5•3•0•0•Updated Dec 10, 2024Dec 10, 2024

    • riscv-ap-tee-io

      Public
      This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.
      tee-io
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •5•10•8•0•Updated Dec 4, 2024Dec 4, 2024

    • riscv-arch-test-reports

      Public
      HTML
      •6•11•0•0•Updated Dec 2, 2024Dec 2, 2024

    • rvv-intrinsic-doc

      Public
      C
      •
      BSD 3-Clause "New" or "Revised" License
      •90•305•20•4•Updated Nov 19, 2024Nov 19, 2024

    • riscv-rqsc

      Public
      Specification Documentation Repository for the RQSC RISC-V Quality of Services Controllers Table definition
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•0•0•1•Updated Nov 18, 2024Nov 18, 2024

    • riscv-acpi-ffh

      Public
      The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•4•1•1•Updated Oct 10, 2024Oct 10, 2024

    • riscv-device-tree-doc

      Public
      RISC-V Specific Device Tree Documentation
      Python
      •3•42•1•1•Updated Jul 9, 2024Jul 9, 2024

    • e-trace-encap

      Public
      E-Trace Encapsulation Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•4•0•1•Updated Jul 5, 2024Jul 5, 2024

    • riscv-iommu-invalidation

      Public
      IOMMU Address Translation Cache Invalidation Commands Extensions
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•0•0•1•Updated May 2, 2024May 2, 2024