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Fix: SWD no-response data phase handling #21

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3 changes: 2 additions & 1 deletion verilog/swdIF.v
Original file line number Diff line number Diff line change
Expand Up @@ -156,7 +156,8 @@ module swdIF (
if (bitcount==PROT_ACK_END) // Have now done
begin
ack <= {swdi,rd[31:30]}; // Store the ACK
if ({swdi,rd[31:30]}==3'b001) // Its a good one
if (({swdi,rd[31:30]}==3'b001) || // Its a good one or
({swdi,rd[31:30]}==3'b111)) // we got no-response
begin
if (rnw) // ..and we're reading
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begin
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