soc/cores/vexriscv_smp: Add the generation of the default sim config (l…

…itex-hub/linux-on-litex-vexriscv#405)

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -211,6 +211,13 @@ def generate_cluster_name():
     # Default Configs Generation.
     @staticmethod
     def generate_default_configs():
+        # Sim
+        VexRiscvSMP.wishbone_memory = False
+        VexRiscvSMP.hardware_breakpoints = 1
+        VexRiscvSMP.coherent_dma = False
+        VexRiscvSMP.generate_cluster_name()
+        VexRiscvSMP.generate_netlist()
+
         # Single cores.
         for data_width in [None, 16, 32, 64, 128]:
             if data_width is None:
@@ -249,6 +256,8 @@ def generate_default_configs():
             VexRiscvSMP.dcache_width   = 32 if data_width is None \
                                               or data_width < 64 else 64
 
+            VexRiscvSMP.hardware_breakpoint = 0
+
             # Without DMA.
             VexRiscvSMP.coherent_dma = False
             VexRiscvSMP.generate_cluster_name()