Merge pull request #1825 from enjoy-digital/verilog_improvements

Verilog improvements

litex/build/altera/platform.py

@@ -38,8 +38,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
-
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/anlogic/platform.py

@@ -31,7 +31,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/colognechip/platform.py

@@ -28,7 +28,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/efinix/platform.py

@@ -56,8 +56,11 @@ def __init__(self, *args, iobank_info=None, toolchain="efinity", spi_mode="activ
     def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         so = dict(common.efinix_special_overrides)
         so.update(special_overrides)
-        return GenericPlatform.get_verilog(self, *args, special_overrides=so,
-            attr_translate=self.toolchain.attr_translate, **kwargs)
+        return GenericPlatform.get_verilog(self, *args,
+            special_overrides = so,
+            attr_translate    = self.toolchain.attr_translate,
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/gowin/platform.py

@@ -38,7 +38,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/lattice/platform.py

@@ -42,7 +42,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/microsemi/platform.py

@@ -29,7 +29,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
+            **kwargs
+        )
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)

litex/build/sim/verilator.py

@@ -228,7 +228,7 @@ def build(self, platform, fragment,
             # Generate verilog
             v_output = platform.get_verilog(fragment,
                 name         = build_name,
-                regular_comb = regular_comb
+                regular_comb = regular_comb,
             )
             named_sc, named_pc = platform.resolve_signals(v_output.ns)
             v_file = build_name + ".v"

litex/build/xilinx/platform.py

@@ -88,7 +88,8 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
         return GenericPlatform.get_verilog(self, *args,
             special_overrides = so,
             attr_translate    = self.toolchain.attr_translate,
-            **kwargs)
+            **kwargs
+        )
 
     def get_edif(self, fragment, **kwargs):
         return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)

litex/gen/common.py

@@ -8,7 +8,7 @@
 
 # Coloring Helpers ---------------------------------------------------------------------------------
 
-def colorer(s, color="bright"):
+def colorer(s, color="bright", enable=True):
     """Apply ANSI colors to a string."""
     header  = {
         "bright": "\x1b[1m",
@@ -18,7 +18,7 @@ def colorer(s, color="bright"):
         "yellow": "\x1b[33m",
         "underline": "\x1b[4m"}[color]
     trailer = "\x1b[0m"
-    return header + str(s) + trailer
+    return (header + str(s) + trailer) if enable else str(s)
 
 # Bit/Bytes Reversing ------------------------------------------------------------------------------
 

litex/gen/context.py

@@ -19,9 +19,9 @@ class LiteXContext:
         platform  : The FPGA Platform of the project.
         toolchain : The FPGA Toolchain to be used for synthesis and place-and-route.
         device    : The FPGA Device of the LiteX project.
-        soc       : The FPGA SoC of the LiteX project.
+        top       : The FPGA Top-Level Module of the LiteX project.
     """
     platform  = None
     toolchain = None
     device    = None
-    soc       = None
+    top       = None

litex/gen/fhdl/hierarchy.py

@@ -14,15 +14,20 @@ class LiteXHierarchyExplorer:
     tree_ident      = "│    "
     tree_entry      = "└─── "
 
-    def __init__(self, top, depth=None):
-        self.top   = top
-        self.depth = depth
+    def __init__(self, top, depth=None, with_colors=True):
+        self.top         = top
+        self.depth       = depth
+        self.with_colors = with_colors
 
-    def get_tree(self, module, ident=0, with_modules=True, with_instances=True):
+    def _colorer(self, s, color="bright"):
+        return colorer(s=s, color=color, enable=self.with_colors)
+
+    def get_tree(self, module, ident=0, with_modules=True, with_instances=True, with_colors=True):
         r = ""
         names = set()
         names.add(None)
-        # Modules / SubModules.
+
+        # Modules / Sub-Modules.
         for name, mod in module._submodules:
             if name is None:
                 n = 0
@@ -31,7 +36,7 @@ def get_tree(self, module, ident=0, with_modules=True, with_instances=True):
                     n += 1
             names.add(name)
             if with_modules:
-                r += f"{self.tree_ident*ident}{self.tree_entry}{colorer(name, 'cyan')} ({mod.__class__.__name__})\n"
+                r += f"{self.tree_ident*ident}{self.tree_entry}{self._colorer(name, 'cyan')} ({mod.__class__.__name__})\n"
             if (self.depth is None) or (ident < self.depth):
                 r += self.get_tree(mod, ident + 1)
 
@@ -44,13 +49,16 @@ def get_tree(self, module, ident=0, with_modules=True, with_instances=True):
                         if s in v._fragment.specials:
                             show = False
                     if show:
-                        r +=  f"{self.tree_ident*ident}{self.tree_entry}{colorer(f'[{s.of}]', 'yellow')}\n"
+                        r +=  f"{self.tree_ident*ident}{self.tree_entry}{self._colorer(f'[{s.of}]', 'yellow')}\n"
         return r
 
-    def __repr__(self):
-        r = "\n"
-        r += f"{colorer(self.top.__class__.__name__, 'underline')}\n"
+    def get_hierarchy(self):
+        r = ""
+        r += f"{self._colorer(self.top.__class__.__name__, 'underline')}\n"
         r += self.get_tree(self.top)
-        r += f"{colorer('* ', 'cyan')}: Generated name.\n"
-        r += f"{colorer('[]', 'yellow')}: BlackBox.\n"
+        r += f"{self._colorer('* ',   'cyan')}: Generated name.\n"
+        r += f"{self._colorer('[]', 'yellow')}: BlackBox.\n"
         return r
+
+    def __repr__(self):
+        return f"\n{self.get_hierarchy()}"

litex/gen/fhdl/instance.py

@@ -0,0 +1,103 @@
+#
+# This file is part of LiteX (Adapted from Migen for LiteX usage).
+#
+# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <[email protected]>
+# This file is Copyright (c) 2023 Florent Kermarrec <[email protected]>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen.fhdl.structure import *
+from migen.fhdl.verilog   import _printexpr as verilog_printexpr
+from migen.fhdl.specials  import *
+
+# Helpers ------------------------------------------------------------------------------------------
+
+def get_max_name_length(ios):
+    r = 0
+    for io in ios:
+        if len(io.name) > r:
+            r = len(io.name)
+    return r
+
+# LiteX Instance Verilog Generation ----------------------------------------------------------------
+
+def _instance_generate_verilog(instance, ns, add_data_file):
+    r = ""
+
+    # Instance Description.
+    # ---------------------
+    r += "//" + "-"*78 + "\n"
+    r += f"// Instance {ns.get_name(instance)} of {instance.of} Module.\n"
+    r += "//" + "-"*78 + "\n"
+
+    # Instance Name.
+    # --------------
+    r += instance.of + " "
+
+    # Instance Parameters.
+    # --------------------
+    parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items))
+    ident      = get_max_name_length(parameters)
+    if parameters:
+        r += "#(\n"
+        first = True
+        r += "\t// Parameters.\n"
+        for p in parameters:
+            if not first:
+                r += ",\n"
+            first = False
+            r += f"\t.{p.name}{' '*(ident-len(p.name))} ("
+            # Constant.
+            if isinstance(p.value, Constant):
+                r += verilog_printexpr(ns, p.value)[0]
+            # Float.
+            elif isinstance(p.value, float):
+                r += str(p.value)
+            # Preformatted.
+            elif isinstance(p.value, Instance.PreformattedParam):
+                r += p.value
+            # String.
+            elif isinstance(p.value, str):
+                r += f"\"{p.value}\""
+            else:
+                raise TypeError
+            r += ")"
+        r += "\n) "
+
+    # Instance IOs.
+    # -------------
+    r += ns.get_name(instance)
+    if parameters:
+        r += " "
+    r += "("
+    inputs  = list(filter(lambda i: isinstance(i, Instance.Input),  instance.items))
+    outputs = list(filter(lambda i: isinstance(i, Instance.Output), instance.items))
+    inouts  = list(filter(lambda i: isinstance(i, Instance.InOut),  instance.items))
+    first   = True
+    ident   = get_max_name_length(inputs + outputs + inouts)
+    for io in (inputs + outputs + inouts):
+        if not first:
+            r += ",\n"
+        if len(inputs) and (io is inputs[0]):
+            r += "\n\t// Inputs.\n"
+        if len(outputs) and (io is outputs[0]):
+            r += "\n\t// Outputs.\n"
+        if len(inouts) and (io is inouts[0]):
+            r += "\n\t// InOuts.\n"
+        name_inst   = io.name
+        name_design = verilog_printexpr(ns, io.expr)[0]
+        first = False
+        r += f"\t.{name_inst}{' '*(ident-len(name_inst))} ({name_design})"
+    if not first:
+        r += "\n"
+
+    # Instance Synthesis Directive.
+    # -----------------------------
+    if instance.synthesis_directive is not None:
+        synthesis_directive = f"/* synthesis {instance.synthesis_directive} */"
+        r += f"){synthesis_directive};\n"
+    else:
+        r += ");\n"
+
+    r += "\n"
+
+    return r

litex/gen/fhdl/memory.py

@@ -2,18 +2,19 @@
 # This file is part of LiteX (Adapted from Migen for LiteX usage).
 #
 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <[email protected]>
-# This file is Copyright (c) 2021 Florent Kermarrec <[email protected]>
+# This file is Copyright (c) 2021-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from migen.fhdl.structure import *
-from migen.fhdl.module import *
+from migen.fhdl.structure    import *
+from migen.fhdl.module       import *
 from migen.fhdl.bitcontainer import bits_for
-from migen.fhdl.tools import *
-from migen.fhdl.verilog import _printexpr as verilog_printexpr
-from migen.fhdl.specials import *
+from migen.fhdl.tools        import *
+from migen.fhdl.verilog      import _printexpr as verilog_printexpr
+from migen.fhdl.specials     import *
 
+# LiteX Memory Verilog Generation ------------------------------------------------------------------
 
-def memory_emit_verilog(name, memory, namespace, add_data_file):
+def _memory_generate_verilog(name, memory, namespace, add_data_file):
     # Helpers.
     # --------