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stream: Switch back to LiteX FIFO, but add an additional output buffe…
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…r, seems to be working...
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enjoy-digital committed Jul 27, 2023
1 parent 86b4447 commit 27fde8b
Showing 1 changed file with 18 additions and 14 deletions.
32 changes: 18 additions & 14 deletions litex/soc/interconnect/stream.py
Original file line number Diff line number Diff line change
Expand Up @@ -281,25 +281,29 @@ def __init__(self, layout, depth, buffered):
#from verilog_axis.axis_async_fifo import AXISAsyncFIFO
#AXISAsyncFIFO.add_sources(platform)

class AsyncFIFO(_AsyncFIFOWrapper):
#class AsyncFIFO(_AsyncFIFOWrapper):
# def __init__(self, layout, depth=None, buffered=False):
# depth = 4 if depth is None else depth
# assert depth >= 4
# buffered = True
# _AsyncFIFOWrapper.__init__(self,
# layout = layout,
# depth = depth,
# buffered = buffered
# )

class AsyncFIFO(_FIFOWrapper):
def __init__(self, layout, depth=None, buffered=False):
depth = 4 if depth is None else depth
assert depth >= 4
buffered = True
_AsyncFIFOWrapper.__init__(self,
buffered = True # FIXME: Required on Efinix...
_FIFOWrapper.__init__(self,
fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
layout = layout,
depth = depth,
buffered = buffered
depth = depth
)

#class AsyncFIFO(_FIFOWrapper):
# def __init__(self, layout, depth=None, buffered=False):
# depth = 4 if depth is None else depth
# assert depth >= 4
# _FIFOWrapper.__init__(self,
# fifo_class = fifo.AsyncFIFOBuffered if buffered else fifo.AsyncFIFO,
# layout = layout,
# depth = depth)
# FIXME: Additional buffer required on Efinix...
ClockDomainsRenamer("read")(BufferizeEndpoints({"source": DIR_SOURCE})(self))

# ClockDomainCrossing ------------------------------------------------------------------------------

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