Skip to content

Actions: enjoy-digital/litex

Actions

All workflows

Actions

Loading...
Loading

Showing runs from all workflows
896 workflow runs
896 workflow runs

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

CHANGES.md: Update. ci #3340: Commit 5f463db pushed by enjoy-digital
October 17, 2024 15:45 24m 57s urv
urv
October 17, 2024 15:45 24m 57s
soc/cores/cpu/urv: Move ROM init to builder and allow switching betwe… ci #3339: Commit aab8912 pushed by enjoy-digital
October 17, 2024 15:44 26m 11s urv
urv
October 17, 2024 15:44 26m 11s
soc/cores/cpu: Add initial uRV CPU support (not yet working). ci #3338: Commit edb56e7 pushed by enjoy-digital
October 16, 2024 20:24 25m 18s urv
urv
October 16, 2024 20:24 25m 18s
Build diamond addition ci #3337: Pull request #2097 opened by trabucayre
October 16, 2024 11:49 25m 23s trabucayre:build_diamond_addition
trabucayre:build_diamond_addition
October 16, 2024 11:49 25m 23s
CHANGES.md: Update. ci #3336: Commit c82fddf pushed by enjoy-digital
October 15, 2024 10:54 25m 19s master
master
October 15, 2024 10:54 25m 19s
soc/core/vexiiriscv : bring back xilinx support ci #3335: Commit d5e4f9e pushed by Dolu1990
October 15, 2024 07:36 24m 47s master
master
October 15, 2024 07:36 24m 47s
soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location require… ci #3334: Commit 7f04caf pushed by trabucayre
October 10, 2024 15:28 25m 21s master
master
October 10, 2024 15:28 25m 21s
CHANGES.md: Update. ci #3333: Commit dc3364a pushed by enjoy-digital
October 9, 2024 14:42 25m 53s master
master
October 9, 2024 14:42 25m 53s
Merge pull request #2095 from trabucayre/zynqmp_ethernet_sgmii ci #3332: Commit 01c7a78 pushed by enjoy-digital
October 9, 2024 14:38 25m 53s master
master
October 9, 2024 14:38 25m 53s
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with optional PTP support ci #3331: Pull request #2095 opened by trabucayre
October 9, 2024 14:17 25m 48s trabucayre:zynqmp_ethernet_sgmii
trabucayre:zynqmp_ethernet_sgmii
October 9, 2024 14:17 25m 48s
Merge pull request #2093 from mgaggero/feature-alpine-linux ci #3330: Commit 34b98ab pushed by trabucayre
October 9, 2024 04:32 25m 58s master
master
October 9, 2024 04:32 25m 58s
Merge pull request #2090 from VOGL-electronic/efinix_iobank ci #3328: Commit bc3e90c pushed by trabucayre
October 8, 2024 07:54 25m 48s master
master
October 8, 2024 07:54 25m 48s
build: efinix: use ifacewriter to set bank voltage ci #3327: Pull request #2090 opened by maass-hamburg
October 8, 2024 07:06 26m 5s VOGL-electronic:efinix_iobank
VOGL-electronic:efinix_iobank
October 8, 2024 07:06 26m 5s
Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix ci #3326: Commit 9ad5d21 pushed by enjoy-digital
October 7, 2024 09:06 22m 10s master
master
October 7, 2024 09:06 22m 10s
build: efinix: Tristate fix ci #3325: Pull request #2089 opened by maass-hamburg
October 7, 2024 08:16 21m 48s VOGL-electronic:efinix_tristate_fix
VOGL-electronic:efinix_tristate_fix
October 7, 2024 08:16 21m 48s
soc/integration/soc: Cleanup imports and directly use math.log2/ceil … ci #3324: Commit 64cf925 pushed by enjoy-digital
October 2, 2024 15:10 27m 42s master
master
October 2, 2024 15:10 27m 42s
build: io.py: DDRTristate: check oe2 ci #3323: Pull request #2074 synchronize by maass-hamburg
October 1, 2024 10:17 25m 14s VOGL-electronic:ddrtristate_oe2_ckeck
VOGL-electronic:ddrtristate_oe2_ckeck
October 1, 2024 10:17 25m 14s
build: io: make oe2 of DDRTristate optional ci #3322: Pull request #2068 synchronize by maass-hamburg
October 1, 2024 10:11 24m 47s VOGL-electronic:ddrtristate_oe2_optional
VOGL-electronic:ddrtristate_oe2_optional
October 1, 2024 10:11 24m 47s
build: efinix: allow clk inverting and different in clk on reg tristates ci #3321: Pull request #2087 synchronize by maass-hamburg
October 1, 2024 10:05 25m 16s VOGL-electronic:io_kwargs
VOGL-electronic:io_kwargs
October 1, 2024 10:05 25m 16s
Merge pull request #2086 from VOGL-electronic/build_io_clocksignal ci #3320: Commit 644ef7e pushed by enjoy-digital
October 1, 2024 09:49 25m 3s master
master
October 1, 2024 09:49 25m 3s
build: efinix: allow clk inverting and different in clk on reg tristates ci #3319: Pull request #2087 opened by maass-hamburg
October 1, 2024 07:32 24m 46s VOGL-electronic:io_kwargs
VOGL-electronic:io_kwargs
October 1, 2024 07:32 24m 46s
build: io: don't use mutable object as default value ci #3318: Pull request #2086 opened by maass-hamburg
September 30, 2024 13:23 25m 35s VOGL-electronic:build_io_clocksignal
VOGL-electronic:build_io_clocksignal
September 30, 2024 13:23 25m 35s
core: i2c: add i2c master ci #3317: Pull request #2026 synchronize by maass-hamburg
September 27, 2024 08:48 24m 43s VOGL-electronic:core_litei2c
VOGL-electronic:core_litei2c
September 27, 2024 08:48 24m 43s
core: i2c: add i2c master ci #3316: Pull request #2026 synchronize by maass-hamburg
September 27, 2024 08:46 1m 6s VOGL-electronic:core_litei2c
VOGL-electronic:core_litei2c
September 27, 2024 08:46 1m 6s
core: i2c: add i2c master ci #3315: Pull request #2026 synchronize by maass-hamburg
September 27, 2024 08:44 59s VOGL-electronic:core_litei2c
VOGL-electronic:core_litei2c
September 27, 2024 08:44 59s