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build/sim/core/veril.cpp: Flush and close trace file on finish, fix i… ci #3289: Commit 00f72e1 pushed by enjoy-digital
September 25, 2024 06:54 25m 45s master
master
September 25, 2024 06:54 25m 45s
build: efinix: add function to add ip ci #3288: Pull request #2078 opened by maass-hamburg
September 24, 2024 10:01 25m 6s VOGL-electronic:efinix_add_ipm
VOGL-electronic:efinix_add_ipm
September 24, 2024 10:01 25m 6s
soc/interconnect/stream: Add Delay module. ci #3287: Commit c95a6e0 pushed by enjoy-digital
September 23, 2024 10:23 24m 53s master
master
September 23, 2024 10:23 24m 53s
CHANGES.md: Update. ci #3286: Commit b2f63b3 pushed by enjoy-digital
September 20, 2024 11:00 24m 31s master
master
September 20, 2024 11:00 24m 31s
build: io.py: add QDR input, output and tristate ci #3285: Pull request #2077 synchronize by maass-hamburg
September 19, 2024 13:13 25m 18s VOGL-electronic:add_qdr_gpios
VOGL-electronic:add_qdr_gpios
September 19, 2024 13:13 25m 18s
Merge pull request #2075 from trabucayre/efinix_clkinput_signal ci #3284: Commit baff4c6 pushed by enjoy-digital
September 19, 2024 09:59 24m 48s master
master
September 19, 2024 09:59 24m 48s
Merge pull request #2076 from trabucayre/xc7s_jtag ci #3283: Commit 033ec13 pushed by enjoy-digital
September 19, 2024 09:53 24m 45s master
master
September 19, 2024 09:53 24m 45s
build: io.py: add QDR input, output and tristate ci #3282: Pull request #2077 opened by maass-hamburg
September 19, 2024 09:14 25m 10s VOGL-electronic:add_qdr_gpios
VOGL-electronic:add_qdr_gpios
September 19, 2024 09:14 25m 10s
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported… ci #3281: Commit 6e9dffd pushed by enjoy-digital
September 19, 2024 09:11 25m 29s master
master
September 19, 2024 09:11 25m 29s
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation wi… ci #3280: Commit ad2c3fc pushed by enjoy-digital
September 19, 2024 07:21 27m 40s master
master
September 19, 2024 07:21 27m 40s
build/efinix/common.py: ClkInput: added ClockSignal support ci #3279: Pull request #2075 synchronize by trabucayre
September 19, 2024 07:14 27m 24s trabucayre:efinix_clkinput_signal
trabucayre:efinix_clkinput_signal
September 19, 2024 07:14 27m 24s
Spartan7 jtag support ci #3278: Pull request #2076 opened by trabucayre
September 19, 2024 04:50 26m 53s trabucayre:xc7s_jtag
trabucayre:xc7s_jtag
September 19, 2024 04:50 26m 53s
build/efinix/common.py: ClkInput: added ClockSignal support ci #3277: Pull request #2075 opened by trabucayre
September 18, 2024 13:27 27m 1s trabucayre:efinix_clkinput_signal
trabucayre:efinix_clkinput_signal
September 18, 2024 13:27 27m 1s
build: io.py: DDRTristate: check oe2 ci #3276: Pull request #2074 opened by maass-hamburg
September 18, 2024 13:08 25m 47s VOGL-electronic:ddrtristate_oe2_ckeck
VOGL-electronic:ddrtristate_oe2_ckeck
September 18, 2024 13:08 25m 47s
build: io: make oe2 of DDRTristate optional ci #3275: Pull request #2068 synchronize by maass-hamburg
September 18, 2024 13:06 24m 54s VOGL-electronic:ddrtristate_oe2_optional
VOGL-electronic:ddrtristate_oe2_optional
September 18, 2024 13:06 24m 54s
Merge pull request #1974 from motec-research/dts_zephyr_updates ci #3274: Commit 9bacbe1 pushed by enjoy-digital
September 17, 2024 12:58 26m 11s master
master
September 17, 2024 12:58 26m 11s
litex_setup: use current version of migen ci #3273: Pull request #2073 opened by maass-hamburg
September 16, 2024 10:09 26m 41s VOGL-electronic:update_migen
VOGL-electronic:update_migen
September 16, 2024 10:09 26m 41s
soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexe… ci #3272: Commit a350d2e pushed by enjoy-digital
September 13, 2024 17:33 25m 11s master
master
September 13, 2024 17:33 25m 11s
build/xilinx/vivado: Fix typo. ci #3271: Commit 2a19a61 pushed by enjoy-digital
September 13, 2024 08:39 24m 39s master
master
September 13, 2024 08:39 24m 39s
Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet ci #3270: Commit 9955080 pushed by enjoy-digital
September 13, 2024 06:36 28m 9s master
master
September 13, 2024 06:36 28m 9s
build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for… ci #3269: Commit dc8c1bd pushed by enjoy-digital
September 12, 2024 16:04 25m 31s master
master
September 12, 2024 16:04 25m 31s
integration/soc/add_etherbone: Allow 64-bit support now that validated. ci #3268: Commit 203c981 pushed by enjoy-digital
September 12, 2024 11:39 25m 43s master
master
September 12, 2024 11:39 25m 43s
feature: Support renaming default uart to uart0. ci #3267: Pull request #1641 synchronize by jorislee
September 12, 2024 09:04 25m 33s jorislee:master
jorislee:master
September 12, 2024 09:04 25m 33s
BIOS: Add BOOTP support ci #3266: Pull request #2070 opened by m-byte
September 12, 2024 08:13 26m 29s VOGL-electronic:bios_bootp
VOGL-electronic:bios_bootp
September 12, 2024 08:13 26m 29s
sim: add HW_PREAMBLE_CRC for ethernet ci #3265: Pull request #2069 opened by m-byte
September 12, 2024 08:09 25m 13s VOGL-electronic:fix-sim-ethernet
VOGL-electronic:fix-sim-ethernet
September 12, 2024 08:09 25m 13s