Skip to content

Commit

Permalink
Merge pull request #2 from mattvenn/release
Browse files Browse the repository at this point in the history
default_nettype none
  • Loading branch information
RTimothyEdwards authored Nov 16, 2020
2 parents 523ee53 + e828dcc commit dfef3f5
Show file tree
Hide file tree
Showing 73 changed files with 80 additions and 1 deletion.
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
StriVe housekeeping SPI testbench.
*/
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe housekeeping pass-thru mode SPI testbench.
*/
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/spiflash.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/caravel/tbuart.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
Expand Down
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
1 change: 1 addition & 0 deletions verilog/dv/dummy_slave.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module dummy_slave(
input wb_clk_i,
input wb_rst_i,
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/la_wb/la_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
`timescale 1 ns / 1 ps

`include "la_wb.v"
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// `define DBG

`define STORAGE_BASE_ADR 32'h0100_0000
Expand Down
1 change: 1 addition & 0 deletions verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

`timescale 1 ns / 1 ps

Expand Down
6 changes: 5 additions & 1 deletion verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none


`timescale 1 ns / 1 ps
Expand All @@ -18,6 +19,9 @@ module uart_wb_tb;

wire wb_ack_o;
wire [31:0] wb_dat_o;

wire tbuart_rx;
wire ser_rx;

initial begin
wb_clk_i = 0;
Expand Down Expand Up @@ -146,4 +150,4 @@ module uart_wb_tb;
.ser_rx(ser_rx)
);

endmodule
endmodule
1 change: 1 addition & 0 deletions verilog/gl/DFFRAM.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module DFFRAM(CLK, EN, VPWR, VGND, A, Di, Do, WE);
Expand Down
1 change: 1 addition & 0 deletions verilog/gl/digital_pll.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module digital_pll(dco, enable, osc, resetb, VPWR, VGND, clockp, div, ext_trim);
Expand Down
1 change: 1 addition & 0 deletions verilog/gl/gpio_control_block.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module gpio_control_block(mgmt_gpio_in, mgmt_gpio_oeb, mgmt_gpio_out, pad_gpio_ana_en, pad_gpio_ana_pol, pad_gpio_ana_sel, pad_gpio_holdover, pad_gpio_ib_mode_sel, pad_gpio_in, pad_gpio_inenb, pad_gpio_out, pad_gpio_outenb, pad_gpio_slow_sel, pad_gpio_vtrip_sel, resetn, serial_clock, serial_data_in, serial_data_out, user_gpio_in, user_gpio_oeb, user_gpio_out, VPWR, VGND, pad_gpio_dm);
Expand Down
1 change: 1 addition & 0 deletions verilog/gl/simple_por.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module simple_por(porb_h, vdd3v3, vss, VPWR, VGND);
Expand Down
1 change: 1 addition & 0 deletions verilog/gl/storage.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module storage(mgmt_clk, mgmt_ena_ro, VPWR, VGND, mgmt_addr, mgmt_addr_ro, mgmt_ena, mgmt_rdata, mgmt_rdata_ro, mgmt_wdata, mgmt_wen, mgmt_wen_mask);
Expand Down
1 change: 1 addition & 0 deletions verilog/gl/user_id_programming.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module user_id_programming(vdd1v8, vss, VPWR, VGND, mask_rev);
Expand Down
1 change: 1 addition & 0 deletions verilog/gl/user_proj_example.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */

module user_proj_example(vccd1, vccd2, vdda1, vdda2, vssa1, vssa2, vssd1, vssd2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, VPWR, VGND, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i);
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/DFFRAM.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
`ifndef USE_CUSTOM_DFFRAM

module DFFRAM(
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/DFFRAMBB.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
Building blocks for DFF based RAM compiler for SKY130A
BYTE : 8 memory cells used as a building block for WORD module
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/caravel.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*--------------------------------------------------------------*/
/* caravel, a project harness for the Google/SkyWater sky130 */
/* fabrication process and open source PDK */
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/caravel_clocking.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// This routine synchronizes the

module caravel_clocking(
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/chip_io.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module chip_io(
// Package Pins
inout vddio, // Common padframe/ESD supply
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/clock_div.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Integer-N clock divider */

module clock_div #(
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/convert_gpio_sigs.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Convert the standard set of GPIO signals: input, output, output_enb,
* pullup, and pulldown into the set needed by the s8 GPIO pads:
* input, output, output_enb, input_enb, mode. Note that dm[2] on
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/counter_timer_high.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Simple 32-bit counter-timer for Caravel. */

/* Counter acts as high 32 bits of a 64-bit counter
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/counter_timer_low.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/* Simple 32-bit counter-timer for Caravel. */

/* Counter acts as low 32 bits of a 64-bit counter
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/defines.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// Global parameters

`define MPRJ_IO_PADS 38
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/digital_pll.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// Digital PLL (ring oscillator + controller)
// Technically this is a frequency locked loop, not a phase locked loop.

Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/digital_pll_controller.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// (True) digital PLL
//
// Output goes to a trimmable ring oscillator (see documentation).
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/gpio_control_block.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
*---------------------------------------------------------------------
* See gpio_control_block for description. This module is like
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/gpio_wb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module gpio_wb # (
parameter BASE_ADR = 32'h 2100_0000,
parameter GPIO_DATA = 8'h 00,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/housekeeping_spi.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
//-------------------------------------
// SPI controller for Caravel (PicoSoC)
//-------------------------------------
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/la_wb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module la_wb # (
parameter BASE_ADR = 32'h 2200_0000,
parameter LA_DATA_0 = 8'h00,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/mem_wb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module mem_wb (
`ifdef USE_POWER_PINS
input VPWR,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/mgmt_core.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module mgmt_core (
`ifdef USE_POWER_PINS
inout vdd1v8,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/mgmt_protect.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*----------------------------------------------------------------------*/
/* Buffers protecting the management region from the user region. */
/* This mainly consists of tristate buffers that are enabled by a */
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/mgmt_soc.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/mprj_ctrl.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module mprj_ctrl_wb #(
parameter BASE_ADR = 32'h 2300_0000,
parameter XFER = 8'h 00,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/mprj_io.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module mprj_io #(
parameter AREA1PADS = 18 // Highest numbered pad in area 1
) (
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/pads.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
`ifndef TOP_ROUTING
`define USER1_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/picorv32.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/ring_osc2x13.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// Tunable ring oscillator---synthesizable (physical) version.
//
// NOTE: This netlist cannot be simulated correctly due to lack
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/simple_por.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
`timescale 1 ns / 1 ps

module simple_por(
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/simple_spi_master.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
//----------------------------------------------------------------------------
// Module: simple_spi_master
//
Expand Down
4 changes: 4 additions & 0 deletions verilog/rtl/simpleuart.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
Expand Down Expand Up @@ -44,6 +45,7 @@ module simpleuart_wb # (
wire [31:0] simpleuart_reg_div_do;
wire [31:0] simpleuart_reg_dat_do;
wire [31:0] simpleuart_reg_cfg_do;
wire reg_dat_wait;

wire resetn = ~wb_rst_i;
wire valid = wb_stb_i && wb_cyc_i;
Expand Down Expand Up @@ -125,6 +127,8 @@ module simpleuart (
reg [31:0] send_divcnt;
reg send_dummy;

wire reg_ena_do;

assign reg_div_do = cfg_divider;
assign reg_ena_do = {31'd0, enabled};

Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/spimemio.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* PicoSoC - A simple example SoC using PicoRV32
*
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/sram_1rw1r_32_256_8_sky130.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// OpenRAM SRAM model
// Words: 256
// Word size: 32
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/storage.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none

module storage (
// MGMT_AREA R/W Interface
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/storage_bridge_wb.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module storage_bridge_wb (
// MGMT_AREA R/W WB Interface
input wb_clk_i,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/sysctrl.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module sysctrl_wb #(
parameter BASE_ADR = 32'h2F00_0000,
parameter PWRGOOD = 8'h00,
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/user_id_programming.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
// This module represents an unprogrammed mask revision
// block that is configured with via programming on the
// chip top level. This value is passed to the block as
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/user_proj_example.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
*-------------------------------------------------------------
*
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/user_project_wrapper.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
*-------------------------------------------------------------
*
Expand Down
1 change: 1 addition & 0 deletions verilog/rtl/wb_intercon.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
module wb_intercon #(
parameter DW = 32, // Data Width
parameter AW = 32, // Address Width
Expand Down
1 change: 1 addition & 0 deletions verilog/stubs/sky130_fd_io__top_xres4v2.v
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
`default_nettype none
/*
* Copyright 2020 The SkyWater PDK Authors
*
Expand Down

0 comments on commit dfef3f5

Please sign in to comment.