[DATA] Add full runs of almost all blocks

- Blocks that are to be hand-designed currently have a dummy layout (a box with pins) - This should be sufficient to reproduce/access the current chip floorplan. Top-level routing is a work-in-progress.
efabless · Nov 13, 2020 · 523ee53 · 523ee53
1 parent 191a81d
commit 523ee53
Show file tree

Hide file tree

Showing 9 changed files with 379,608 additions and 0 deletions.
diff --git a/verilog/gl/DFFRAM.v b/verilog/gl/DFFRAM.v
diff --git a/verilog/gl/digital_pll.v b/verilog/gl/digital_pll.v
diff --git a/verilog/gl/gpio_control_block.v b/verilog/gl/gpio_control_block.v
diff --git a/verilog/gl/mgmt_core.v.gz b/verilog/gl/mgmt_core.v.gz
diff --git a/verilog/gl/simple_por.v b/verilog/gl/simple_por.v
@@ -0,0 +1,112 @@
+/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
+
+module simple_por(porb_h, vdd3v3, vss, VPWR, VGND);
+  input VGND;
+  input VPWR;
+  wire _0_;
+  wire mid;
+  output porb_h;
+  input vdd3v3;
+  input vss;
+  sky130_fd_sc_hvl__decap_4 FILLER_0_0 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_8 FILLER_0_12 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_4 FILLER_0_20 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__fill_2 FILLER_0_24 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__fill_1 FILLER_0_26 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__fill_2 FILLER_0_4 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__fill_1 FILLER_0_6 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_4 FILLER_1_0 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_8 FILLER_1_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_4 FILLER_1_23 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_4 FILLER_2_0 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_8 FILLER_2_15 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__decap_4 FILLER_2_23 (
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__conb_1 _1_ (
+    .LO(_0_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR)
+  );
+  sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
+    .A(_0_),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(mid)
+  );
+  sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
+    .A(mid),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(porb_h)
+  );
+endmodule