docs/regmap: General fixes for SystemVerilog regmap package generation (

#1495) docs/regmap: General fixes for SystemVerilog regmap package generation Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
analogdevicesinc · Oct 23, 2024 · 0889fce · 0889fce
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Showing 15 changed files with 200 additions and 137 deletions.
diff --git a/docs/regmap/adi_regmap_axi_laser_driver.txt b/docs/regmap/adi_regmap_axi_laser_driver.txt
@@ -39,7 +39,7 @@ ID
 ENDREG
 
 FIELD
-[31:0] ''ID''
+[31:0] ID
 ID
 RO
 Value of the ID configuration parameter.
@@ -93,7 +93,7 @@ Configuration Registers
 ENDREG
 
 FIELD
-[31:0] ''PULSE_PERIOD''
+[31:0] PULSE_PERIOD
 PWM_PERIOD
 RW
 The period of the generated signal. The resolution is the core clock's time period.
@@ -110,7 +110,7 @@ Configuration Registers
 ENDREG
 
 FIELD
-[31:0] ''PULSE_WIDTH''
+[31:0] PULSE_WIDTH
 PWM_WIDTH
 RW
 The pulse width of the generated signal. The resolution is the core clock's time period.

diff --git a/docs/regmap/adi_regmap_data_offload.txt b/docs/regmap/adi_regmap_data_offload.txt
@@ -39,7 +39,7 @@ PERIPHERAL_ID
 ENDREG
 
 FIELD
-[31:0] ''ID''
+[31:0] ID
 PERIPHERAL_ID
 RO
 Value of the ID configuration parameter.
@@ -84,22 +84,22 @@ SYNTHESIS_CONFIG_1
 ENDREG
 
 FIELD
-[2] ''HAS_BYPASS''
+[2] HAS_BYPASS
 HAS_BYPASS
 RO
 If set the bypass logic is implemented.
 ENDFIELD
 
 FIELD
-[1] ''TX_OR_RXN_PATH''
+[1] TX_OR_RXN_PATH
 TX_OR_RXN_PATH
 RO
 If this device was configured for the TX path, this bit will be set to 1.
 Conversely, the bit will be 0 for the RX path.
 ENDFIELD
 
 FIELD
-[0] ''MEM_TYPE''
+[0] MEM_TYPE
 MEMORY_TYPE
 RO
 This bit identifies the type of memory that was chosen during synthesis. A value of 1
@@ -115,7 +115,7 @@ SYNTHESIS_CONFIG_2
 ENDREG
 
 FIELD
-[31:0] 1<<''MEM_SIZE_LOG2''
+[31:0] MEM_SIZE_LSB = 1<<MEM_SIZE_LOG2
 MEM_SIZE_LSB
 RO
 32 bits (LSB) of the storage unit size. 
@@ -130,7 +130,7 @@ SYNTHESIS_CONFIG_3
 ENDREG
 
 FIELD
-[1:0] (1<<''MEM_SIZE_LOG2'')>>32
+[1:0] MEM_SIZE_MSB = (1<<MEM_SIZE_LOG2)>>32
 MEM_SIZE_MSB
 RO
 2 bits (MSB) of the storage unit size. 
@@ -145,7 +145,7 @@ TRANSFER_LENGTH
 ENDREG
 
 FIELD
-[31:0] (2^''MEM_SIZE_LOG2''-1)>>6
+[31:0] TRANSFER_LENGTH = (2**MEM_SIZE_LOG2-1)>>6
 TRANSFER_LENGTH
 RW
 The transfer length register can be used to override the transfer length in RX mode in increments of 64 bytes.
@@ -189,7 +189,7 @@ RESET_OFFLOAD
 ENDREG
 
 FIELD
-[0] ''AUTO_BRINGUP''
+[0] AUTO_BRINGUP
 RESETN
 RW
 "Software Reset": Resets all the internal address registers and state machines.
@@ -204,7 +204,7 @@ CONTROL
 ENDREG
 
 FIELD
-[1] ~''TX_OR_RXN_PATH''
+[1] ONESHOT_EN = ~TX_OR_RXN_PATH
 ONESHOT_EN
 RW
 Enables oneshot mode. This means that the data offload will only play a received buffer once,
@@ -259,14 +259,14 @@ FSM_BDG
 ENDREG
 
 FIELD
-[11:8] 0xXXXXXXXX
+[11:8]
 FSM_STATE_READ
 RO
 It force the Rx side offload state machine into the required state.
 ENDFIELD
 
 FIELD
-[4:0] 0xXXXXXXXX
+[4:0]
 FSM_STATE_WRITE
 RO
 The current state of the offload state machine.

diff --git a/docs/regmap/adi_regmap_dmac.txt b/docs/regmap/adi_regmap_dmac.txt
@@ -39,7 +39,7 @@ PERIPHERAL_ID
 ENDREG
 
 FIELD
-[31:0] ''ID''
+[31:0] ID
 PERIPHERAL_ID
 RO
 Value of the ID configuration parameter.
@@ -84,35 +84,35 @@ INTERFACE_DESCRIPTION_1
 ENDREG
 
 FIELD
-[3:0] log2(''DMA_DATA_WIDTH_DEST''/8)
+[3:0] BYTES_PER_BEAT_DEST_LOG2 = $clog2(DMA_DATA_WIDTH_DEST/8)
 BYTES_PER_BEAT_DEST_LOG2
 R
 Width of data bus on destination interface. Log2 of interface data widths in bytes.
 ENDFIELD
 
 FIELD
-[5:4] ''DMA_TYPE_DEST''
+[5:4] DMA_TYPE_DEST
 DMA_TYPE_DEST
 R
 Value of ''DMA_TYPE_DEST'' parameter.(0 - AXI MemoryMap, 1 -  AXI Stream, 2 - FIFO )
 ENDFIELD
 
 FIELD
-[11:8] log2(''DMA_DATA_WIDTH_SRC''/8)
+[11:8] BYTES_PER_BEAT_SRC_LOG2 = $clog2(DMA_DATA_WIDTH_SRC/8)
 BYTES_PER_BEAT_SRC_LOG2
 R
 Width of data bus on source interface. Log2 of interface data widths in bytes.
 ENDFIELD
 
 FIELD
-[13:12] ''DMA_TYPE_SRC''
+[13:12] DMA_TYPE_SRC
 DMA_TYPE_SRC
 R
 Value of ''DMA_TYPE_SRC'' parameter.(0 - AXI MemoryMap, 1 -  AXI Stream, 2 - FIFO )
 ENDFIELD
 
 FIELD
-[19:16] ''BYTES_PER_BURST_WIDTH''
+[19:16] BYTES_PER_BURST_WIDTH
 BYTES_PER_BURST_WIDTH
 R
 Value of ''BYTES_PER_BURST_WIDTH'' interface parameter. Log2 of the real ''MAX_BYTES_PER_BURST''.
@@ -129,21 +129,21 @@ INTERFACE_DESCRIPTION_2
 ENDREG
 
 FIELD
-[0] ''CACHE_COHERENT''
+[0] CACHE_COHERENT
 CACHE_COHERENT
 R
 Value of ''CACHE_COHERENT'' parameter.(0 - Disabled, 1 -  Enabled )
 ENDFIELD
 
 FIELD
-[7:4] ''AXI_AXCACHE''
+[7:4] AXI_AXCACHE
 AXI_AXCACHE
 R
 Value of ''AXI_AXCACHE'' parameter.
 ENDFIELD
 
 FIELD
-[10:8] ''AXI_AXPROT''
+[10:8] AXI_AXPROT
 AXI_AXPROT
 R
 Value of ''AXI_AXPROT'' parameter.
@@ -298,7 +298,7 @@ FLAGS
 ENDREG
 
 FIELD
-[0] ''CYCLIC''
+[0] CYCLIC
 CYCLIC
 RW
 Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode
@@ -368,7 +368,7 @@ X_LENGTH
 ENDREG
 
 FIELD
-[31:0] 2^log2(max(''DMA_DATA_WIDTH_SRC'', ''DMA_DATA_WIDTH_DEST'')/8)-1
+[31:0] X_LENGTH = 2**$clog2(`MAX(DMA_DATA_WIDTH_SRC, DMA_DATA_WIDTH_DEST)/8)-1
 X_LENGTH
 RW
 Number of bytes to transfer - 1.

diff --git a/docs/regmap/adi_regmap_fan_control.txt b/docs/regmap/adi_regmap_fan_control.txt
@@ -39,7 +39,7 @@ PERIPHERAL_ID
 ENDREG
 
 FIELD
-[31:0] ''ID''
+[31:0] ID
 PERIPHERAL_ID
 RO
 Value of the ID configuration parameter.
@@ -221,7 +221,7 @@ PWM_WIDTH
 ENDREG
 
 FIELD
-[31:0] ''PWM_PERIOD''
+[31:0] PWM_PERIOD
 PWM_WIDTH
 RW
 This register contains the width of the PWM output signal. By default its
@@ -278,7 +278,7 @@ TEMP_DATA_SOURCE
 ENDREG
 
 FIELD
-[31:0] ''INTERNAL_SYSMONE''
+[31:0] INTERNAL_SYSMONE
 TEMP_DATA_SOURCE
 RO
 This register copies the value from the INTERNAL_SYSMONE register and is used to inform
@@ -342,7 +342,7 @@ TEMP_00_H
 ENDREG
 
 FIELD
-[31:0] ''TEMP_00_H''
+[31:0] TEMP_00_H
 TEMP_00_H
 RW
 Temperature threshold below which PWM should be 0%
@@ -357,7 +357,7 @@ TEMP_25_L
 ENDREG
 
 FIELD
-[31:0] ''TEMP_25_L''
+[31:0] TEMP_25_L
 TEMP_25_L
 RW
 Temperature threshold above which PWM should be 25%
@@ -372,7 +372,7 @@ TEMP_25_H
 ENDREG
 
 FIELD
-[31:0] ''TEMP_25_H''
+[31:0] TEMP_25_H
 TEMP_25_H
 RW
 Temperature threshold below which PWM should be 25%
@@ -387,7 +387,7 @@ TEMP_50_L
 ENDREG
 
 FIELD
-[31:0] ''TEMP_50_L''
+[31:0] TEMP_50_L
 TEMP_50_L
 RW
 Temperature threshold above which PWM should be 50%
@@ -402,7 +402,7 @@ TEMP_50_H
 ENDREG
 
 FIELD
-[31:0] ''TEMP_50_H''
+[31:0] TEMP_50_H
 TEMP_50_H
 RW
 Temperature threshold below which PWM should be 50%
@@ -417,7 +417,7 @@ TEMP_75_L
 ENDREG
 
 FIELD
-[31:0] ''TEMP_75_L''
+[31:0] TEMP_75_L
 TEMP_75_L
 RW
 Temperature threshold above which PWM should be 75%
@@ -432,7 +432,7 @@ TEMP_75_H
 ENDREG
 
 FIELD
-[31:0] ''TEMP_75_H''
+[31:0] TEMP_75_H
 TEMP_75_H
 RW
 Temperature threshold below which PWM should be 75%
@@ -447,7 +447,7 @@ TEMP_100_L
 ENDREG
 
 FIELD
-[31:0] ''TEMP_100_L''
+[31:0] TEMP_100_L
 TEMP_100_L
 RW
 Temperature threshold above which PWM should be 100%
@@ -462,7 +462,7 @@ TACHO_25
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T25''
+[31:0] TACHO_T25
 TACHO_25
 RW
 Nominal tacho period at 25% PWM
@@ -477,7 +477,7 @@ TACHO_50
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T50''
+[31:0] TACHO_T50
 TACHO_50
 RW
 Nominal tacho period at 50% PWM
@@ -492,7 +492,7 @@ TACHO_75
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T75''
+[31:0] TACHO_T75
 TACHO_75
 RW
 Nominal tacho period at 75% PWM
@@ -507,7 +507,7 @@ TACHO_100
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T100''
+[31:0] TACHO_T100
 TACHO_100
 RW
 Nominal tacho period at 100% PWM
@@ -522,7 +522,7 @@ TACHO_25_TOL
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T25''*''TACHO_TOL_PERCENT''/100
+[31:0] TACHO_25_TOL = TACHO_T25*TACHO_TOL_PERCENT/100
 TACHO_25_TOL
 RW
 Tolerance for the 25% PWM tacho period
@@ -537,7 +537,7 @@ TACHO_50_TOL
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T50''*''TACHO_TOL_PERCENT''/100
+[31:0] TACHO_50_TOL = TACHO_T50*TACHO_TOL_PERCENT/100
 TACHO_50_TOL
 RW
 Tolerance for the 50% PWM tacho period
@@ -552,7 +552,7 @@ TACHO_75_TOL
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T75''*''TACHO_TOL_PERCENT''/100
+[31:0] TACHO_75_TOL = TACHO_T75*TACHO_TOL_PERCENT/100
 TACHO_75_TOL
 RW
 Tolerance for the 75% PWM tacho period
@@ -567,7 +567,7 @@ TACHO_100_TOL
 ENDREG
 
 FIELD
-[31:0] ''TACHO_T100''*''TACHO_TOL_PERCENT''/100
+[31:0] TACHO_100_TOL = TACHO_T100*TACHO_TOL_PERCENT/100
 TACHO_100_TOL
 RW
 Tolerance for the 100% PWM tacho period