RISC-V small fix: Disable traps by clearing XIE CSR #7078
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Ensure we disable traps by clearing XIE CSR instead of clearing XSTATUS.IE which is global interrupt enable bit. Signed-off-by: Alvin Chang <[email protected]> Reviewed-by: Yu Chien Peter Lin <[email protected]>
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Ensure we disable traps by clearing XIE CSR instead of clearing XSTATUS.IE which is global interrupt enable bit.