change direction of BRAM

build.sbt

@@ -4,7 +4,7 @@ ThisBuild / scalaVersion := "2.13.12"
 ThisBuild / version := "0.1.0"
 ThisBuild / organization := "org.hyperdbg"
 
-val chiselVersion = "6.0.0"
+val chiselVersion = "6.2.0"
 
 lazy val root = (project in file("."))
   .settings(

src/main/scala/hwdbg/main.scala

@@ -49,11 +49,10 @@ class DebuggerMain(
     //
     // BRAM (Block RAM) ports
     //
-    val rdAddr = Input(UInt(bramAddrWidth.W)) // read address
-    val rdData = Output(UInt(bramDataWidth.W)) // read data
-    val wrAddr = Input(UInt(bramAddrWidth.W)) // write address
-    val wrEna = Input(Bool()) // enable writing
-    val wrData = Input(UInt(bramDataWidth.W)) // write data
+    val rdWrAddr = Output(UInt(bramAddrWidth.W)) // read/write address
+    val rdData = Input(UInt(bramDataWidth.W)) // read data
+    val wrEna = Output(Bool()) // enable writing
+    val wrData = Output(UInt(bramDataWidth.W)) // write data
 
   })
 
@@ -65,7 +64,9 @@ class DebuggerMain(
   }
 
   io.psOutInterrupt := false.B
-  io.rdData := 0.U
+  io.rdWrAddr := 0.U
+  io.wrEna := false.B
+  io.wrData := 0.U
 }
 
 object DebuggerMain {
@@ -79,12 +80,9 @@ object DebuggerMain {
   )(
       en: Bool,
       inputPin: Vec[UInt],
-      psOutInterrupt: Bool,
-      rdAddr: UInt,
-      wrAddr: UInt,
-      wrEna: Bool,
-      wrData: UInt
-  ): (Vec[UInt], Bool, UInt) = {
+      plInSignal: Bool,
+      rdData: UInt
+  ): (Vec[UInt], Bool, UInt, Bool, UInt) = {
 
     val debuggerMainModule = Module(
       new DebuggerMain(
@@ -98,28 +96,30 @@ object DebuggerMain {
 
     val outputPin = Wire(Vec(numberOfOutputPins, UInt((1.W))))
     val psOutInterrupt = Wire(Bool())
-    val rdData = Wire(UInt(bramDataWidth.W))
+    val rdWrAddr = Wire(UInt(bramAddrWidth.W))
+    val wrEna = Wire(Bool())
+    val wrData = Wire(UInt(bramDataWidth.W))
 
     //
     // Configure the input signals
     //
     debuggerMainModule.io.en := en
     debuggerMainModule.io.inputPin := inputPin
-    debuggerMainModule.io.rdAddr := rdAddr
-    debuggerMainModule.io.wrAddr := wrAddr
-    debuggerMainModule.io.wrEna := wrEna
-    debuggerMainModule.io.wrData := wrData
+    debuggerMainModule.io.plInSignal := plInSignal
+    debuggerMainModule.io.rdData := rdData
 
     //
     // Configure the input signals
     //
     outputPin := debuggerMainModule.io.outputPin
     psOutInterrupt := debuggerMainModule.io.psOutInterrupt
-    rdData := debuggerMainModule.io.rdData
+    rdWrAddr := debuggerMainModule.io.rdWrAddr
+    wrEna := debuggerMainModule.io.wrEna
+    wrData := debuggerMainModule.io.wrData
 
     //
     // Return the output result
     //
-    (outputPin, psOutInterrupt, rdData)
+    (outputPin, psOutInterrupt, rdWrAddr, wrEna, wrData)
   }
 }

src/main/scala/top.scala

@@ -48,18 +48,17 @@ class DebuggerModule(
     //
     // BRAM (Block RAM) ports
     //
-    val rdAddr = Input(UInt(bramAddrWidth.W)) // read address
-    val rdData = Output(UInt(bramDataWidth.W)) // read data
-    val wrAddr = Input(UInt(bramAddrWidth.W)) // write address
-    val wrEna = Input(Bool()) // enable writing
-    val wrData = Input(UInt(bramDataWidth.W)) // write data
+    val rdWrAddr = Output(UInt(bramAddrWidth.W)) // read/write address
+    val rdData = Input(UInt(bramDataWidth.W)) // read data
+    val wrEna = Output(Bool()) // enable writing
+    val wrData = Output(UInt(bramDataWidth.W)) // write data
 
   })
 
   //
   // Instantiate the debugger's main module
   //
-  val (outputPin, psOutInterrupt, rdData) =
+  val (outputPin, psOutInterrupt, rdWrAddr, wrEna, wrData) =
     DebuggerMain(
       debug,
       numberOfInputPins,
@@ -70,15 +69,14 @@ class DebuggerModule(
       io.en,
       io.inputPin,
       io.plInSignal,
-      io.rdAddr,
-      io.wrAddr,
-      io.wrEna,
-      io.wrData
+      io.rdData
     )
 
   io.outputPin := outputPin
   io.psOutInterrupt := psOutInterrupt
-  io.rdData := rdData
+  io.rdWrAddr := rdWrAddr
+  io.wrEna := wrEna
+  io.wrData := wrData
 
 }
 

src/main/scala/top_test.scala

@@ -57,6 +57,8 @@ class DebuggerModuleTestingBRAM(
   val bramAddr = WireInit(0.U(bramAddrWidth.W))
   val bramDataIn = WireInit(0.U(bramDataWidth.W))
 
+  val bramDataOut = WireInit(0.U(bramDataWidth.W))
+
   //
   // Instantiate the BRAM memory initializer module
   //
@@ -74,10 +76,12 @@ class DebuggerModuleTestingBRAM(
       bramDataIn
     )
 
+  bramDataOut := dataOut
+
   //
   // Instantiate the debugger's main module
   //
-  val (outputPin, psOutInterrupt, rdData) =
+  val (outputPin, psOutInterrupt, rdWrAddr, wrEna, wrData) =
     DebuggerMain(
       debug,
       numberOfInputPins,
@@ -88,14 +92,46 @@ class DebuggerModuleTestingBRAM(
       io.en,
       io.inputPin,
       io.plInSignal,
-      bramAddr,
-      bramAddr,
-      bramEn,
-      dataOut
+      bramDataOut
     )
 
+  //
+  // Connect BRAM Pins
+  //
+  bramEn := io.en // enable BRAM when the main chip enabled
+  bramAddr := rdWrAddr
+  bramWrite := wrEna
+  bramDataIn := wrData
+
+  //
+  // Connect I/O pins
+  //
   io.outputPin := outputPin
   io.psOutInterrupt := psOutInterrupt
-  bramDataIn := rdData
 
 }
+
+object MainWithInitializedBRAM extends App {
+
+  //
+  // Generate hwdbg verilog files
+  //
+  println(
+    ChiselStage.emitSystemVerilog(
+      new DebuggerModuleTestingBRAM(
+        DebuggerConfigurations.ENABLE_DEBUG,
+        DebuggerConfigurations.NUMBER_OF_INPUT_PINS,
+        DebuggerConfigurations.NUMBER_OF_OUTPUT_PINS,
+        DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+        DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+      ),
+      firtoolOpts = Array(
+        "-disable-all-randomization",
+        "-strip-debug-info",
+        "--split-verilog", // The intention for this argument (and next argument) is to separate generated files.
+        "-o",
+        "generated/"
+      )
+    )
+  )
+}