change buffer initialization

HyperDbg · Apr 4, 2024 · 11f3eda · 11f3eda
1 parent b02264d
commit 11f3eda
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Showing 2 changed files with 8 additions and 5 deletions.
diff --git a/src/main/scala/hwdbg/libs/mem/init_mem.scala b/src/main/scala/hwdbg/libs/mem/init_mem.scala
@@ -21,7 +21,7 @@ import hwdbg.configs._
 
 class InitMemInline(
     debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
-    memoryFile: String = "",
+    memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
     addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
     width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
     size: Int =
@@ -58,7 +58,7 @@ object InitMemInline {
 
   def apply(
       debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
-      memoryFile: String = "",
+      memoryFile: String = TestingConfigurations.BRAM_INITIALIZATION_FILE_PATH,
       addrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
       width: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
       size: Int =

diff --git a/src/main/scala/hwdbg/main.scala b/src/main/scala/hwdbg/main.scala
@@ -60,9 +60,12 @@ class DebuggerMain(
   //
   // Used for testing verilog generation, should be removed
   //
-  io.outputPin := io.inputPin
-  io.psOutInterrupt := io.plInSignal
-  io.rdAddr := io.rdData | io.wrAddr | io.wrData | io.wrEna
+  for (i <- 0 until numberOfOutputPins) {
+    io.outputPin(i) := 0.U
+  }
+
+  io.psOutInterrupt := false.B
+  io.rdData := 0.U
 }
 
 object DebuggerMain {