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fix memory sink holes
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SinaKarvandi committed Apr 4, 2024
1 parent cd860a0 commit b02264d
Showing 1 changed file with 5 additions and 1 deletion.
6 changes: 5 additions & 1 deletion src/main/scala/hwdbg/main.scala
Original file line number Diff line number Diff line change
Expand Up @@ -57,8 +57,12 @@ class DebuggerMain(

})

//
// Used for testing verilog generation, should be removed
//
io.outputPin := io.inputPin

io.psOutInterrupt := io.plInSignal
io.rdAddr := io.rdData | io.wrAddr | io.wrData | io.wrEna
}

object DebuggerMain {
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