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arm: refactor test92 to avoid conflicting writes and add possibly conflicting reads #162
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arm: refactor test92 to avoid conflicting writes and add possibly conflicting reads #162
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I would keep the original logic of storing the result of loads.
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Wouldn't this require then memory barriers to be added?, moving the store outside of the critical loop seems to work, but without a memory barrier it might get reordered and would cause failures (although not as obvious, as the infinite loop)
When refactoring, I thought about using a second array for the stores, but with a possible granule of 512 words, it will need ugly tricks to keep it safe anyway.
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On ARM the doc says in "Load-Acquire, Store-Release" section:
Load-Acquire.
Store-Release instruction.
If barriers needs to be added on some cpus, the instruction should implicitly add them.
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Note that (even before LSE and other future improvements) in aarch64 there are 2 pairs of instructions for its LL/SC.
Our implementation uses the weak (and better performing) pair of
ldxr
/stxr
but their semantics don't correspond to what is used on other processors and that seem to map[1] better to the strong (and slower) pair (ldaxr
/stlxr
).Not that anyone should, but if someone would implement a futex or mutex with sljit, it might work fine in x86/s390x and break with ARM (and probably the other RISC CPUs if implemented using LL/SC).
I have to admit that without a clear understanding on how this API is to be used, I am not sure if it is a problem but it might be something worth considering by maybe adding a "weak" parameter that would be a NOOP in strong ordered architectures and allow selecting the right pair in weak ordered ones like ARM.
If this is to be modeled like C11/C++11 atomics then maybe a full set of memory_order options might be needed instead.
[1] https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html