Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

dts: renesas_ra: Changing to describe clocks with DeviceTree's standard manner #78365

Merged
merged 6 commits into from
Oct 8, 2024
Merged

dts: renesas_ra: Changing to describe clocks with DeviceTree's standard manner #78365

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
528f6a1
west.yml: Update revision of hal_renesas
soburi Sep 12, 2024
0206c84
devicetree: Adding UNQUOTED, TOKEN, and UPPERTOKEN variants of FULL_NAME
soburi Sep 12, 2024
3358e07
dts: renesas_ra: Rename dts node path
soburi Sep 11, 2024
20d359f
dts: renesas_ra: Referencing clocks change to DeviceTree's standard.
soburi Sep 12, 2024
45a141f
dts: renesas_ra: Change to describe the division ratio in a numeric
soburi Sep 12, 2024
9c5ef6b
drivers: clock_control: renesas_ra: Adding macros to convert DT values
soburi Sep 12, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra4e2/ek_ra4e2.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
clocks = <&xtal>;
div = <1>;
mul = <10 0>;
status = "okay";
};
Expand Down
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra4m2/ek_ra4m2.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
clocks = <&xtal>;
div = <3>;
mul = <25 0>;
status = "okay";
};
Expand Down
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra4m3/ek_ra4m3.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
clocks = <&xtal>;
div = <3>;
mul = <25 0>;
status = "okay";
};
Expand Down
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra6e2/ek_ra6e2.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -94,8 +94,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
clocks = <&xtal>;
div = <1>;
mul = <10 0>;
status = "okay";
};
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra6m1/ek_ra6m1.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -60,8 +60,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
clocks = <&xtal>;
div = <1>;
mul = <20 0>;
status = "okay";
};
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra6m2/ek_ra6m2.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -60,8 +60,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
clocks = <&xtal>;
div = <1>;
mul = <20 0>;
status = "okay";
};
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra6m3/ek_ra6m3.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -72,8 +72,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
clocks = <&xtal>;
div = <2>;
mul = <20 0>;
status = "okay";
};
8 changes: 4 additions & 4 deletions boards/renesas/ek_ra6m4/ek_ra6m4.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,14 +68,14 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
clocks = <&xtal>;
div = <3>;
mul = <25 0>;
status = "okay";
};

&pclka {
clk-src = <RA_CLOCK_SOURCE_PLL>;
clk-div = <RA_SYS_CLOCK_DIV_2>;
clocks = <&pll>;
div = <2>;
status = "okay";
};
4 changes: 2 additions & 2 deletions boards/renesas/ek_ra6m5/ek_ra6m5.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,8 +68,8 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
clocks = <&xtal>;
div = <3>;
mul = <25 0>;
status = "okay";
};
14 changes: 7 additions & 7 deletions boards/renesas/ek_ra8d1/ek_ra8d1.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -56,21 +56,21 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
clocks = <&xtal>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "okay";
};

&sciclk {
clk-src = <RA_CLOCK_SOURCE_PLL1P>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
clocks = <&pll>;
div = <4>;
status = "okay";
};

Expand Down
14 changes: 7 additions & 7 deletions boards/renesas/ek_ra8m1/ek_ra8m1.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -79,21 +79,21 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
clocks = <&xtal>;
div = <2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "okay";
};

&sciclk {
clk-src = <RA_CLOCK_SOURCE_PLL1P>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
clocks = <&pll>;
div = <4>;
status = "okay";
};

Expand Down
4 changes: 2 additions & 2 deletions boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -57,8 +57,8 @@
};

&pll {
source = <RA_PLL_SOURCE_HOCO>;
div = <RA_PLL_DIV_2>;
clocks = <&hoco>;
div = <2>;
mul = <20 0>;
status = "okay";
};
Expand Down
4 changes: 2 additions & 2 deletions boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -76,8 +76,8 @@
};

&pll {
source = <RA_PLL_SOURCE_HOCO>;
div = <RA_PLL_DIV_1>;
clocks = <&hoco>;
div = <1>;
mul = <10 0>;
status = "okay";
};
14 changes: 7 additions & 7 deletions boards/renesas/mck_ra8t1/mck_ra8t1.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -60,21 +60,21 @@
};

&pll {
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
clocks = <&xtal>;
div = <2>;
mul = <80 0>;
divp = <RA_PLL_DIV_2>;
divp = <2>;
freqp = <DT_FREQ_M(480)>;
divq = <RA_PLL_DIV_2>;
divq = <2>;
freqq = <DT_FREQ_M(480)>;
divr = <RA_PLL_DIV_2>;
divr = <2>;
freqr = <DT_FREQ_M(480)>;
status = "okay";
};

&sciclk {
clk-src = <RA_CLOCK_SOURCE_PLL1P>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
clocks = <&pll>;
div = <4>;
status = "okay";
};

Expand Down
9 changes: 5 additions & 4 deletions drivers/clock_control/clock_control_renesas_ra_cgc.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -90,10 +90,11 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = {
#define INIT_PCLK(node_id) \
IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \
(static const struct clock_control_ra_pclk_cfg node_id##_cfg = \
{.clk_src = DT_PROP_OR(node_id, clk_src, \
DT_PROP_OR(DT_PARENT(node_id), sysclock_src, \
RA_CLOCK_SOURCE_DISABLE)), \
.clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \
{.clk_src = COND_CODE_1( \
DT_NODE_HAS_PROP(node_id, clocks), \
(RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(node_id))), \
(RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_PARENT(node_id))))), \
.clk_div = RA_CGC_CLK_DIV(node_id, div, 1)}; \
DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL, \
&node_id##_cfg, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, \
Expand Down
12 changes: 6 additions & 6 deletions dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@
#address-cells = <1>;
#size-cells = <1>;

xtal: clock-xtal {
xtal: clock-main-osc {
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(12)>;
#clock-cells = <0>;
Expand Down Expand Up @@ -64,33 +64,33 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
clocks = <&hoco>;
status = "okay";

iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};

pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};

pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};

fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_1>;
div = <1>;
#clock-cells = <2>;
status = "okay";
};
Expand Down
20 changes: 10 additions & 10 deletions dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@
#address-cells = <1>;
#size-cells = <1>;

xtal: clock-xtal {
xtal: clock-main-osc {
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(20)>;
#clock-cells = <0>;
Expand Down Expand Up @@ -83,8 +83,8 @@
#clock-cells = <0>;

/* PLL */
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
clocks = <&xtal>;
div = <1>;
mul = <10 0>;
status = "disabled";
};
Expand All @@ -96,47 +96,47 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
clocks = <&pll>;
status = "okay";

iclk: iclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};

pclka: pclka {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};

pclkb: pclkb {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

pclkc: pclkc {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};

pclkd: pclkd {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_2>;
div = <2>;
#clock-cells = <2>;
status = "okay";
};

fclk: fclk {
compatible = "renesas,ra-cgc-pclk";
clk-div = <RA_SYS_CLOCK_DIV_4>;
div = <4>;
#clock-cells = <2>;
status = "okay";
};
Expand Down
Loading
Loading