Add support Flash QSPI on S32Z270 #78073
Conversation
zephyrbot
added
area: MEMC
area: Settings
zephyrbot
requested review from
bperseghetti,
carlescufi,
Dat-NguyenDuy,
dcpleung,
de-nordic,
jakub-uC,
kartben,
Laczen,
nashif,
nordic-krch and
PetervdPerk-NXP
|
The following west manifest projects have changed revision in this Pull Request:
⛔ DNM label due to: 1 project with PR revision Note: This message is automatically posted and updated by the Manifest GitHub Action. |
zephyrbot
added
manifest
manifest-hal_nxp
DNM
congnguyenhuu
changed the title
congnguyenhuu
force-pushed
the
nxp-s32ze-support-flash-qspi
branch
from
eb86fa0 to
a517164
Compare
|
I rebased to fix conflict west manifest |
|
Don't worry about the west.yml conflict. Since we have a block of HAL PRs merging this will constantly be a problem @congnguyenhuu couple of things to respond/resolve:
|
congnguyenhuu
force-pushed
the
nxp-s32ze-support-flash-qspi
branch
2 times, most recently
from
94697af to
115465c
Compare
|
Hello @danieldegrasse, Could you help me to review these changes. Thanks. |
|
@congnguyenhuu please fix the ci failures. |
congnguyenhuu
dismissed stale reviews from manuargue, Dat-NguyenDuy, and danieldegrasse
via
33ab075
congnguyenhuu
force-pushed
the
nxp-s32ze-support-flash-qspi
branch
from
115465c to
33ab075
Compare
|
Hello, I rebased to fix the CI check failure, but the current bsim test check is failing based on the latest code. Therefore, I logged issue #83388 to fix. |
Following the commit f98fde0, DT_REG_ADDR now expands with a 'U' suffix as an unsigned value. However, for compatibility with IS_EQ, a raw value without any suffix is required. Therefore, this update is necessary. Signed-off-by: Cong Nguyen Huu <[email protected]>
Add support QSPI secure flash protection (SFP) Signed-off-by: Cong Nguyen Huu <[email protected]>
Create common source code to use for supporting HyperFlash. Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to 'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig. Add the 'max-program-buffer-size' property to use for setting memory pageSize, instead of using 'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting. Add the 'write-block-size' propertyto use for setting the number of bytes used in write operations, it also uses to instead of the 'memory-alignment' property. Signed-off-by: Cong Nguyen Huu <[email protected]>
Add support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver. Driver allows to read, write and erase HyperFlash devices. Signed-off-by: Cong Nguyen Huu <[email protected]>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller. Signed-off-by: Cong Nguyen Huu <[email protected]>
Enable flash samples for s32z board Signed-off-by: Cong Nguyen Huu <[email protected]>
Enable flash tests for s32z board Signed-off-by: Cong Nguyen Huu <[email protected]>
congnguyenhuu
force-pushed
the
nxp-s32ze-support-flash-qspi
branch
from
33ab075 to
e2c6a90
Compare
|
Hello @de-nordic, the CI failure is fixed, could you please revisit. Thanks. |
|
Hello @de-nordic, Could you please review the changes again? We need your approval as the assignee to merge the HAL PR first, so we can update the west manifest file before merging this PR. Thanks. |
|
@dleach02 can you please help us move forward with this merge? this PR have been approved a few times already and the HAL pr is also approved. Thanks |
There was a problem hiding this comment.
Needs to be sequenced behind #81012
@congnguyenhuu I merged the HAL side. After the gating PR merges, then we can update the HAL SHA and I'll clear my CR
Introduce support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver and allows to read, write, and erase HyperFlash devices.
Add support QSPI secure flash protection (SFP) for memory control NXP S32 QSPI.
Enable support Flash QSPI on S32Z2XX, the on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller.
The test result: