-
Notifications
You must be signed in to change notification settings - Fork 6.8k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
hwmv2: Port renesas socs/boards #68705
hwmv2: Port renesas socs/boards #68705
Conversation
The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
89b1dfa
to
58a85a1
Compare
@@ -1,4 +1,4 @@ | |||
identifier: rcar_spider_cr52 | |||
identifier: rcar_spider_s4 | |||
name: Cortex r52 for Renesas Spider |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Note: There will be support for ARM64 Spider S4 (based on Cortex A55)
the arm64 spider pr is blocked for now due to toher changes related to Spider S4
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
We're in the feature freeze process for 3.6 and the timeline is that hwmv2 will be merged as soon as the 3.6 release is done, so any new boards/socs being added should be done using hwmv2 as hwmv1 will not be accepted. For this to support the other core, it just needs the soc.yml file updating with a cpucluster
entry to have both cores, then the files here would be renamed to have the CPU names in and you can build for them using -DBOARD=rcar_spider_s4/<cpu>
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I meant to say that you've connected the Spider S4 board to the Cortex R52 in name.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
The yaml will need to be updated when the other core is added to have the CPU identifier so will become rcar_spider_s4_<cpu>.yaml
and identifier will match that
config NUM_IRQS | ||
default 512 | ||
default 512 if SOC_R8A77951_R7 | ||
default 240 if SOC_R8A77961 || SOC_R8A77951_A57 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
you may align the number of IRQs with R7, actually it is the same according to documentation 480 SPI and 32 PPI+SGI
bool | ||
select SOC_FAMILY_RENESAS_RCAR | ||
help | ||
Renesas R-Car Gen4 Cortex R52 |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
all series have a specific Cortex R core, look like we need to avoid it
soc/renesas/rzt2m/CMakeLists.txt
Outdated
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I believe that the dir architecture should be another for the RZ, like soc/renesas/rz/t
or soc/renesas/rz/a
, moreover it will be aligned with rz dts dir (https://github.com/zephyrproject-rtos/zephyr/tree/main/dts/arm/renesas/rz)
look at renesas doc page: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
This is how it is named in the current zephyr tree, if you would like it changed that is fine but I request that you submit a PR for it after this is merged, there's about 640 boards in total to convert in a very short time frame and I don't have time available to make changes for vendors to each of them
Could you please add appropriate changes to the MAINTAINER file to Renesas sections? |
This will be done en masse once all boards and socs have been ported in the branch |
8862241
to
ef8ad68
Compare
2c3624b
to
2456fd8
Compare
2456fd8
to
bdc40d7
Compare
Updates the folder structure to allow for more SoCs to be added, and fixes some minor issues Signed-off-by: Jamie McCrae <[email protected]>
Ports the rcar SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Ports the smartbond SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <[email protected]>
Updates for changes with hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Ports the ra SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Converts the board to hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Updates board names which have changed with hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
Updates paths to account for changes in hwmv2 Signed-off-by: Jamie McCrae <[email protected]>
bdc40d7
to
719c7e0
Compare
55cfded
into
zephyrproject-rtos:collab-hwm
No description provided.