Renesas: Smartbond: Add MEMC Driver Support #68023
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zephyrbot
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area: MEMC
area: Samples
zephyrbot
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andrzej-kaczmarek,
galak,
kartben,
nashif and
nordic-krch
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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ydamigos
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May 15, 2024
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| qspi_set_read_pipe_delay(7); | ||
| qspi_set_cs_delay(SystemCoreClock, | ||
| da1469x_qspi_set_read_pipe_delay(QSPIC_ID, 7); | ||
| da1469x_qspi_set_cs_delay(QSPIC_ID, SystemCoreClock, | ||
| DT_PROP(DT_NODELABEL(flash_controller), | ||
| read_cs_idle_delay), | ||
| DT_PROP(DT_NODELABEL(flash_controller), | ||
| erase_cs_idle_delay)); | ||
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(memc), okay) | ||
| da1469x_qspi_set_read_pipe_delay(QSPIC2_ID, 7); | ||
| da1469x_qspi_set_cs_delay(QSPIC2_ID, SystemCoreClock, | ||
| DT_PROP(DT_NODELABEL(memc), read_cs_idle_min_ns), | ||
| DT_PROP_OR(DT_NODELABEL(memc), erase_cs_idle_min_ns, 0)); | ||
| #if DT_PROP(DT_NODELABEL(memc), is_ram) | ||
| da1469x_qspi_set_tcem(SystemCoreClock, DT_PROP(DT_NODELABEL(memc), tcem_max_us)); | ||
| #endif | ||
| #endif |
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Should we move it to a separate function? Code looks the same like in lines 381-395.
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Correct. Applying memory settings has been moved to a subroutine.
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ydamigos
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May 16, 2024
blauret
previously approved these changes
May 16, 2024
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@kartben, Could you kindly review again!!! I think we are there with this one. |
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@andrzej-kaczmarek ping |
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May 22, 2024
| type: int | ||
| required: true | ||
| description: | | ||
| Time in microsends (us) the memory device can accept the next command following a SW reset. |
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Suggested change
| Time in microsends (us) the memory device can accept the next command following a SW reset. | |
| Time in microseconds (us) the memory device can accept the next command following a SW reset. |
| access in case the total time exceeds the defined value | ||
| (at the cost of extra cycles required for re-sending the instruction, | ||
| address and dummy bytes, if any). This setting is meaningful only if | ||
| is-ram is present. This value reflects the max. time in microsends the |
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Suggested change
| is-ram is present. This value reflects the max. time in microsends the | |
| is-ram is present. This value reflects the max. time in microseconds the |
| type: int | ||
| required: true | ||
| description: | | ||
| Manafacturer ID, part of device ID, used to verify the memory device used. |
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Suggested change
| Manafacturer ID, part of device ID, used to verify the memory device used. | |
| Manufacturer ID, part of device ID, used to verify the memory device used. |
| type: boolean | ||
| description: | | ||
| If present, the memory device will enter the QPI mode which typically reflects that | ||
| all bytes be sent in qaud bus mode. It's a pre-requisite that read and write |
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Suggested change
| all bytes be sent in qaud bus mode. It's a pre-requisite that read and write | |
| all bytes be sent in quad bus mode. It's a pre-requisite that read and write |
| default: "addr-range-24bit" | ||
| description: | | ||
| Address size to use in auto mode. In 24-bit mode up to 16MB can be | ||
| accessed whilst in 32-bit mode up to 32MB can be accssed which is |
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Suggested change
| accessed whilst in 32-bit mode up to 32MB can be accssed which is | |
| accessed whilst in 32-bit mode up to 32MB can be accessed which is |
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| Describes the mode of SPI bus during the dummy bytes phase for single/burst | ||
| read accesses in auto mode. The single mode should be supported by all | ||
| memory devices. |
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Suggested change
| Describes the mode of SPI bus during the dummy bytes phase for single/burst | |
| read accesses in auto mode. The single mode should be supported by all | |
| memory devices. | |
| Describes the mode of SPI bus during the dummy bytes phase for single/burst | |
| read accesses in auto mode. Default value is single mode which should be supported by all | |
| memory devices. |
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| Describes the mode of SPI bus during the extra byte phase for single/burst | ||
| read accesses in auto mode. The single mode should be supported by all | ||
| memory devices. |
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Suggested change
| Describes the mode of SPI bus during the extra byte phase for single/burst | |
| read accesses in auto mode. The single mode should be supported by all | |
| memory devices. | |
| Describes the mode of SPI bus during the extra byte phase for single/burst | |
| read accesses in auto mode. Default value is single mode which should be supported by all | |
| memory devices. |
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| Describes the mode of SPI bus during the address phase for single/burst | ||
| write accesses in auto mode. The single mode should be supported by all | ||
| memory devices. |
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Suggested change
| Describes the mode of SPI bus during the address phase for single/burst | |
| write accesses in auto mode. The single mode should be supported by all | |
| memory devices. | |
| Describes the mode of SPI bus during the address phase for single/burst | |
| write accesses in auto mode. Default value is single mode which should be supported by all | |
| memory devices. |
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| write accesses in auto mode. The single mode should be supported by all | ||
| memory devices. |
There was a problem hiding this comment.
Suggested change
| write accesses in auto mode. The single mode should be supported by all | |
| memory devices. | |
| write accesses in auto mode. Default value is single mode which should be supported by all | |
| memory devices. |
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| Describes the mode of SPI bus during the data phase for single/burst | ||
| write accesses in auto mode. The single mode should be supported by all | ||
| memory devices. |
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Suggested change
| Describes the mode of SPI bus during the data phase for single/burst | |
| write accesses in auto mode. The single mode should be supported by all | |
| memory devices. | |
| Describes the mode of SPI bus during the data phase for single/burst | |
| write accesses in auto mode. Default value is single mode which should be supported by all | |
| memory devices. |
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Fixed all typos
Add support for the memory controller by utilizing QSPIC2. The latter is capable to drive both NOR and PSRAM memory devices. For this to work, the RAM driving mode is enabled. Signed-off-by: Ioannis Karachalios <[email protected]>
1. Update the clock control driver so it can update timing settings for QSPIC2 following system clock transitions (translated based on AHB AMBA bus clock). 2. Remove the QSPIC related subroutines and use the respective HAL API which is now available. 3. Add support for PM (CONFIG_PM_DEVICE). This is required as QSPIC2 register file is powered by PD_SYS which is turned off during device sleep and so registers contents are lost (in contrast to QSPIC which is used to drive the flash memory). Signed-off-by: Ioannis Karachalios <[email protected]>
Update DTS and board configurations to support memory controller (QSPIC2). Signed-off-by: Ioannis Karachalios <[email protected]>
In order to avoid defining almost the same overlays in the available sample codes, tests and user applications, a common overlay file per memory type is demonstrated under the boards dts folder. Currently only the PSRAM interface is supported and the APS6404L PSRAM QSPI memory device is demonstrated. In doing so, an application code will only have to define another overlay file explicitly, under application's board folder, to overwrite the default QSPI controller's settings. In either case, users should explicitly invoke the requested overlay files at 'west build' invokation via the DTC_OVERLAY_FILE system variable. Signed-off-by: Ioannis Karachalios <[email protected]>
Add configuration and overlay files to support the DA1469x development kit. Signed-off-by: Ioannis Karachalios <[email protected]>
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blauret
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Add configuration and overlay files to support the DA1469x development kit. Signed-off-by: Ioannis Karachalios <[email protected]>
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