drivers: watchdog: sam0: initialize GCLK2 in wdt_sam0_init

Initialize GCLK2 to output 1.024kHz required by watchdog timer. Co-authored-by: Vlad Laba7 <[email protected]> Signed-off-by: Gerson Fernando Budke <[email protected]>
zephyrproject-rtos · Jan 20, 2024 · d996fb8 · d996fb8
1 parent 18c23de
commit d996fb8
Showing 1 changed file with 19 additions and 0 deletions.
diff --git a/soc/arm/atmel_sam0/common/soc_samd2x.c b/soc/arm/atmel_sam0/common/soc_samd2x.c
@@ -246,6 +246,24 @@ static inline void gclk_adc_configure(void)
 }
 #endif
 
+#if !CONFIG_WDT_SAM0
+#define gclk_wdt_configure()
+#else
+static inline void gclk_wdt_configure(void)
+{
+	GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)
+			 | GCLK_GENDIV_DIV(4);
+
+	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2)
+			  | GCLK_GENCTRL_GENEN
+			  | GCLK_GENCTRL_SRC_OSCULP32K
+			  | GCLK_GENCTRL_DIVSEL;
+
+	while (GCLK->STATUS.bit.SYNCBUSY) {
+	}
+}
+#endif
+
 #if CONFIG_SOC_ATMEL_SAMD_OSC8M || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
 #define osc8m_disable()
 #else
@@ -265,5 +283,6 @@ void z_arm_platform_init(void)
 	flash_waitstates_init();
 	gclk_main_configure();
 	gclk_adc_configure();
+	gclk_wdt_configure();
 	osc8m_disable();
 }