dts: arm: st: c0: add nodes for MCO clocks

This commit adds nodes for MCO clocks for the STM32C0 series.
Also adds macros for selecting source and division of the MCO clocks.

Adding the following to the nucleo_c031c6 board dts while running
the hello_world sample gives an output clock of 6 MHz on PA9 from
dividing the 48 MHz HSE with 8:

&clk_mco {
	clocks = <&rcc 0 MCO_DIV(3)>,
		 <&rcc 0 MCO_SEL(4)>;
	pinctrl-0 = <&rcc_mco_pa9>;
	pinctrl-names = "default";
	status = "okay";
};

Signed-off-by: Benjamin Björnsson <[email protected]>

dts/arm/st/c0/stm32c0.dtsi

@@ -64,6 +64,16 @@
 			clock-frequency = <DT_FREQ_K(32)>;
 			status = "disabled";
 		};
+
+		clk_mco: clk-mco {
+			compatible = "st,stm32-mco-clock";
+			status = "disabled";
+		};
+
+		clk_mco2: clk-mco2 {
+			compatible = "st,stm32-mco-clock";
+			status = "disabled";
+		};
 	};
 
 	soc {

include/zephyr/dt-bindings/clock/stm32c0_clock.h

@@ -57,13 +57,21 @@
 	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
 	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
 
+/** @brief RCC_CFGRR register offset */
+#define CFGR_REG		0x08
+
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x54
 
 /** @brief RCC_CSR1 register offset */
 #define CSR1_REG		0x5C
 
 /** @brief Device domain clocks selection helpers */
+/** CFGR devices */
+#define MCO_SEL(val)		STM32_CLOCK(val, 3, 24, CFGR_REG)
+#define MCO_DIV(val)		STM32_CLOCK(val, 3, 28, CFGR_REG)
+#define MCO2_SEL(val)		STM32_CLOCK(val, 3, 16, CFGR_REG)
+#define MCO2_DIV(val)		STM32_CLOCK(val, 3, 20, CFGR_REG)
 /** CCIPR devices */
 #define USART1_SEL(val)		STM32_CLOCK(val, 3, 0, CCIPR_REG)
 #define I2C1_SEL(val)		STM32_CLOCK(val, 3, 12, CCIPR_REG)