dts: arm: Enabling pit for imx devices

Enabled the PIT and Multi channel support for some of the rtXXXX devices. - rt1010 - rt1060 - rt1160 - rt1170 Signed-off-by: Emilio Benavente <[email protected]>
zephyrproject-rtos · Mar 7, 2024 · 9815296 · 9815296
1 parent 8bb95d3
commit 9815296
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Showing 16 changed files with 256 additions and 9 deletions.
diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2023 TiaC Systems
- * Copyright 2019,2023 NXP
+ * Copyright 2019,2023-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -176,3 +176,7 @@ zephyr_udc0: &usb1 {
 &systick {
 	status = "okay";
 };
+
+&pit0 {
+	status = "okay";
+};
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NXP
+ * Copyright 2018,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -288,3 +288,7 @@ arduino_spi: &lpspi1 {
 &pxp {
 	status = "okay";
 };
+
+&pit0 {
+	status = "okay";
+};
diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NXP
+ * Copyright 2021,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -100,3 +100,11 @@ zephyr_udc0: &usb1 {
 &mailbox_a {
 	status = "okay";
 };
+
+&pit1 {
+	status = "okay";
+};
+
+&pit2 {
+	status = "okay";
+};
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-22, NXP
+ * Copyright 2021-2022,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -148,3 +148,11 @@ zephyr_udc0: &usb1 {
 &mailbox_a {
 	status = "okay";
 };
+
+&pit1 {
+	status = "okay";
+};
+
+&pit2 {
+	status = "okay";
+};
diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NXP
+ * Copyright 2017,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -326,6 +326,11 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 	case IMX_CCM_FLEXSPI2_CLK:
 		*rate = CLOCK_GetClockRootFreq(kCLOCK_Flexspi2ClkRoot);
 		break;
+#endif
+#ifdef CONFIG_COUNTER_NXP_PIT
+	case IMX_CCM_PIT_CLK:
+		*rate = CLOCK_GetFreq(kCLOCK_PerClk);
+		break;
 #endif
 	}
 

diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NXP
+ * Copyright 2021,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -140,6 +140,11 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 	case IMX_CCM_FLEXSPI2_CLK:
 		clock_root = kCLOCK_Root_Flexspi2;
 		break;
+#endif
+#ifdef CONFIG_COUNTER_NXP_PIT
+	case IMX_CCM_PIT_CLK:
+		clock_root = kCLOCK_Root_Bus + instance;
+		break;
 #endif
 	default:
 		return -EINVAL;

diff --git a/dts/arm/nxp/nxp_rt1010.dtsi b/dts/arm/nxp/nxp_rt1010.dtsi
@@ -386,3 +386,7 @@
 &gpio5{
 	pinmux = <&iomuxc_snvs_pmic_on_req_gpio5_io00>;
 };
+
+&pit0 {
+	interrupts = <24 0>;
+};
diff --git a/dts/arm/nxp/nxp_rt10xx.dtsi b/dts/arm/nxp/nxp_rt10xx.dtsi
@@ -1087,6 +1087,41 @@
 			reg = <0x400d8000 0x2a0>;
 			status = "disabled";
 		};
+
+		pit0: pit@40084000 {
+			compatible = "nxp,pit";
+			reg = <0x40084000 0x1000>;
+			clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
+			interrupts = <122 0>;
+			max-load-value = <0xffffffff>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pit0_channel0: pit0_channel@0 {
+				compatible = "nxp,pit-channel";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			pit0_channel1: pit0_channel@1 {
+				compatible = "nxp,pit-channel";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			pit0_channel2: pit0_channel@2 {
+				compatible = "nxp,pit-channel";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			pit0_channel3: pit0_channel@3 {
+				compatible = "nxp,pit-channel";
+				reg = <3>;
+				status = "disabled";
+			};
+		};
 	};
 };
 

diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi
@@ -1127,6 +1127,72 @@
 			status = "disabled";
 		};
 
+		pit1: pit@400D8000 {
+			compatible = "nxp,pit";
+			reg = <0x400D8000 0x4000>;
+			clocks = <&ccm IMX_CCM_PIT_CLK 0x0 0>;
+			interrupts = <155 0>;
+			max-load-value = <0xffffffff>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pit1_channel0: pit1_channel@0 {
+				compatible = "nxp,pit-channel";
+				reg = <0>;
+				status = "disabled";
+			};
+
+			pit1_channel1: pit1_channel@1 {
+				compatible = "nxp,pit-channel";
+				reg = <1>;
+				status = "disabled";
+			};
+
+			pit1_channel2: pit1_channel@2 {
+				compatible = "nxp,pit-channel";
+				reg = <2>;
+				status = "disabled";
+			};
+
+			pit1_channel3: pit1_channel@3 {
+				compatible = "nxp,pit-channel";
+				reg = <3>;
+				status = "disabled";
+			};
+		};
+
+		pit2: pit@40CB0000 {
+			compatible = "nxp,pit";
+			reg = <0x40CB0000 0x4000>;
+			clocks = <&ccm IMX_CCM_PIT1_CLK 0x0 0>;
+			interrupts = <156 0>;
+			max-load-value = <0xffffffff>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pit2_channel0: pit2_channel@0 {
+				compatible = "nxp,pit-channel";
+				reg = <0>;
+				status = "disabled";
+				};
+			pit2_channel1: pit2_channel@1 {
+				compatible = "nxp,pit-channel";
+				reg = <1>;
+				status = "disabled";
+				};
+			pit2_channel2: pit2_channel@2 {
+				compatible = "nxp,pit-channel";
+				reg = <2>;
+				status = "disabled";
+			};
+			pit2_channel3: pit2_channel@3 {
+				compatible = "nxp,pit-channel";
+				reg = <2>;
+				status = "disabled";
+			};
+		};
 	};
 };
 

diff --git a/include/zephyr/dt-bindings/clock/imx_ccm.h b/include/zephyr/dt-bindings/clock/imx_ccm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2022, NXP
+ * Copyright 2017-2022,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -61,4 +61,6 @@
 #define IMX_CCM_FLEXSPI_CLK		0x0F00UL
 #define IMX_CCM_FLEXSPI2_CLK		0x0F01UL
 
+#define IMX_CCM_PIT_CLK                 0x1000UL
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */
diff --git a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NXP
+ * Copyright 2021,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -95,5 +95,8 @@
 /* FLEXSPI */
 #define IMX_CCM_FLEXSPI_CLK	0x4000UL
 #define IMX_CCM_FLEXSPI2_CLK	0x4001UL
+/* PIT */
+#define IMX_CCM_PIT_CLK                 0x5000UL
+#define IMX_CCM_PIT1_CLK                0x5001UL
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */
diff --git a/soc/nxp/imxrt/imxrt11xx/soc.c b/soc/nxp/imxrt/imxrt11xx/soc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2023 NXP
+ * Copyright 2021-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -346,6 +346,10 @@ static ALWAYS_INLINE void clock_init(void)
 	rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
 	rootCfg.div = 4;
 	CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
+#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
+	rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
 #endif
 
 	/* Configure CSSYS using OSC_RC_48M_DIV2 */

diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1010_evk.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1010_evk.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pit0_channel0 {
+	status = "okay";
+};
+
+&pit0_channel1 {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk.overlay
@@ -1,3 +1,23 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pit0_channel0 {
+	status = "okay";
+};
+
+&pit0_channel1 {
+	status = "okay";
+};
+
+/* channel 2 disabled to test disabled channel not breaking things */
+
+&pit0_channel3 {
+	status = "okay";
+};
+
 &qtmr1_timer0 {
 	status = "okay";
 	primary_source = "kQTMR_ClockDivide_128";

diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pit1_channel0 {
+	status = "okay";
+};
+
+&pit1_channel1 {
+	status = "okay";
+};
+
+/* channel 2 disabled to test disabled channel not breaking things */
+
+&pit1_channel3 {
+	status = "okay";
+};
+
+&pit2_channel0 {
+	status = "okay";
+};
+
+&pit2_channel1 {
+	status = "okay";
+};
+
+/* channel 2 disabled to test disabled channel not breaking things */
+
+&pit2_channel3 {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pit1_channel0 {
+	status = "okay";
+};
+
+&pit1_channel1 {
+	status = "okay";
+};
+
+/* channel 2 disabled to test disabled channel not breaking things */
+
+&pit1_channel3 {
+	status = "okay";
+};
+
+&pit2_channel0 {
+	status = "okay";
+};
+
+&pit2_channel1 {
+	status = "okay";
+};
+
+/* channel 2 disabled to test disabled channel not breaking things */
+
+&pit2_channel3 {
+	status = "okay";
+};
-Original file line number
+Diff line change
@@ Expand Up / @@ -386,3 +386,7 @@ @@
     &gpio5{
     	pinmux = <&iomuxc_snvs_pmic_on_req_gpio5_io00>;
     };
+    &pit0 {
+    	interrupts = <24 0>;
+    };