soc: intel_adsp: hwmv2: Align SOC_SERIES_INTEL_ACE name and value

Align `ace` to 'intel_adsp_ace` SoC Series name and value to match the new HWMv2 compliance check, also renaming: SOC_SERIES_INTEL_ACE --> SOC_SERIES_INTEL_ADSP_ACE Signed-off-by: Dmitrii Golovanov <[email protected]>
zephyrproject-rtos · Feb 23, 2024 · 608ba1d · 608ba1d
1 parent d282a2b
commit 608ba1d
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Showing 23 changed files with 66 additions and 64 deletions.
diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c
@@ -570,7 +570,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
 	dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index);
 
 	for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 		dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL,
 				     CIC_CONTROL_SOFT_RESET, 0);
 
@@ -621,7 +621,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
 				     FIELD_PREP(FIR_CONTROL_START, start_fir));
 	}
 
-#ifndef CONFIG_SOC_SERIES_INTEL_ACE
+#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	/* Clear soft reset for all/used PDM controllers. This should
 	 * start capture in sync.
 	 */

diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c
@@ -175,7 +175,7 @@ static int dai_nhlt_update_rate(struct dai_intel_dmic *dmic, const int clock_sou
 	return 0;
 }
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic,
 				    int *count, int pdm_count, int stereo,
 				    int source_pdm)
@@ -426,7 +426,7 @@ static inline int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const ui
 static int print_outcontrol(uint32_t val)
 {
 	int bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8;
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	int bf9, bf10, bf11, bf12, bf13;
 #endif
 	uint32_t ref;
@@ -447,7 +447,7 @@ static int print_outcontrol(uint32_t val)
 		return -EINVAL;
 	}
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val);
 	bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val);
 	bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val);
@@ -487,7 +487,7 @@ static void print_cic_control(uint32_t val)
 	bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val);
 	bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val);
 	bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val);
-#ifndef CONFIG_SOC_SERIES_INTEL_ACE
+#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val);
 #else
 	bf7 = -1;
@@ -503,7 +503,7 @@ static void print_cic_control(uint32_t val)
 		FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) |
 		FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) |
 		FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6)
-#ifndef CONFIG_SOC_SERIES_INTEL_ACE
+#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 		| FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7)
 #endif
 		;
@@ -520,7 +520,7 @@ static void print_fir_control(uint32_t val)
 
 	bf1 = FIELD_GET(FIR_CONTROL_START, val);
 	bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val);
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val);
 #else
 	bf3 = -1;
@@ -534,7 +534,7 @@ static void print_fir_control(uint32_t val)
 	LOG_DBG("  dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
 	ref = FIELD_PREP(FIR_CONTROL_START, bf1) |
 		FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) |
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 		FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) |
 #endif
 		FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) |
@@ -561,7 +561,7 @@ static void print_pdm_ctrl(const struct nhlt_pdm_ctrl_cfg *pdm_cfg)
 
 	val = pdm_cfg->mic_control;
 
-#ifndef CONFIG_SOC_SERIES_INTEL_ACE
+#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val);
 #else
 	bf1 = -1;
@@ -797,7 +797,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
 		}
 	}
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	ret = dai_nhlt_dmic_dai_params_get(dmic, dmic_cfg->clock_source);
 #else
 	ret = dai_nhlt_dmic_dai_params_get(dmic);

diff --git a/drivers/dai/intel/ssp/Kconfig.ssp b/drivers/dai/intel/ssp/Kconfig.ssp
@@ -15,7 +15,7 @@ config DAI_INTEL_SSP
 
 config DAI_SSP_HAS_POWER_CONTROL
 	bool "DAI ssp pm_runtime en/dis ssp power"
-	default y if SOC_SERIES_INTEL_ACE
+	default y if SOC_SERIES_INTEL_ADSP_ACE
 	depends on DAI_INTEL_SSP
 
 if DAI_INTEL_SSP

diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c
@@ -1634,7 +1634,7 @@ static int dai_ssp_check_aux_data(struct ssp_intel_aux_tlv *aux_tlv, int aux_len
 		size = sizeof(struct ssp_intel_ext_ctl);
 		break;
 	case SSP_LINK_CLK_SOURCE:
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 		size = sizeof(struct ssp_intel_link_ctl);
 		break;
 #else
@@ -1669,7 +1669,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con
 	struct ssp_intel_node_ctl *node;
 	struct ssp_intel_sync_ctl *sync;
 	struct ssp_intel_ext_ctl *ext;
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	struct ssp_intel_link_ctl *link;
 #endif
 	uint8_t *aux_ptr;
@@ -1725,7 +1725,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con
 			LOG_INF("%s ext ext_data %u", __func__, ext->ext_data);
 			break;
 		case SSP_LINK_CLK_SOURCE:
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 			link = (struct ssp_intel_link_ctl *)&aux_tlv->val;
 
 #if CONFIG_SOC_INTEL_ACE15_MTPM

diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h
@@ -236,7 +236,7 @@
 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 /** \brief Offset of MCLK Divider Control Register. */
 #define MN_MDIVCTRL 0x100
 

diff --git a/drivers/dma/Kconfig.intel_adsp_gpdma b/drivers/dma/Kconfig.intel_adsp_gpdma
@@ -21,7 +21,7 @@ config DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP
 
 config DMA_INTEL_ADSP_GPDMA_HAS_LLP
 	bool "Intel ADSP GPDMA Linear Link Position Feature"
-	default y if SOC_SERIES_INTEL_ACE
+	default y if SOC_SERIES_INTEL_ADSP_ACE
 	help
 	  Intel ADSP GPDMA may optionally have a linear link position
 	  feature.

diff --git a/drivers/dma/dma_intel_adsp_gpdma.c b/drivers/dma/dma_intel_adsp_gpdma.c
@@ -163,7 +163,7 @@ static int intel_adsp_gpdma_config(const struct device *dev, uint32_t channel,
 static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel)
 {
 	int ret = 0;
-#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE
+#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	bool first_use = false;
 	enum pm_device_state state;
 
@@ -188,7 +188,7 @@ static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel)
 		intel_adsp_gpdma_llp_disable(dev, channel);
 	}
 
-#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE
+#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	/* Device usage is counted by the calls of dw_dma_start and dw_dma_stop. For the first use,
 	 * we need to make sure that the pm_device_runtime_get and pm_device_runtime_put functions
 	 * calls are balanced.
@@ -247,7 +247,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev)
 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
 	uint32_t val;
 
-	if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE)) {
+	if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)) {
 		val = sys_read32(reg) | GPDMA_CTL_DCGD;
 	} else {
 		val = GPDMA_CTL_FDCGB;
@@ -259,7 +259,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev)
 #ifdef CONFIG_PM_DEVICE
 static void intel_adsp_gpdma_clock_disable(const struct device *dev)
 {
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
 	uint32_t val = sys_read32(reg) & ~GPDMA_CTL_DCGD;
@@ -272,7 +272,7 @@ static void intel_adsp_gpdma_clock_disable(const struct device *dev)
 static void intel_adsp_gpdma_claim_ownership(const struct device *dev)
 {
 #ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
 	uint32_t val = sys_read32(reg) | GPDMA_OSEL(0x3);
@@ -282,15 +282,15 @@ static void intel_adsp_gpdma_claim_ownership(const struct device *dev)
 	sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(0));
 	sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(1));
 	ARG_UNUSED(dev);
-#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
+#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */
 #endif /* CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP */
 }
 
 #ifdef CONFIG_PM_DEVICE
 static void intel_adsp_gpdma_release_ownership(const struct device *dev)
 {
 #ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
 	uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
 	uint32_t val = sys_read32(reg) & ~GPDMA_OSEL(0x3);
@@ -299,12 +299,12 @@ static void intel_adsp_gpdma_release_ownership(const struct device *dev)
 	/* CHECKME: Do CAVS platforms set ownership over DMA,
 	 * if yes, add support for it releasing.
 	 */
-#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
+#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */
 #endif /* CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP */
 }
 #endif
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 static int intel_adsp_gpdma_enable(const struct device *dev)
 {
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
@@ -330,14 +330,14 @@ static int intel_adsp_gpdma_disable(const struct device *dev)
 	return 0;
 }
 #endif /* CONFIG_PM_DEVICE */
-#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
+#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */
 
 static int intel_adsp_gpdma_power_on(const struct device *dev)
 {
 	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
 	int ret;
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	/* Power up */
 	ret = intel_adsp_gpdma_enable(dev);
 
@@ -382,12 +382,12 @@ static int intel_adsp_gpdma_power_off(const struct device *dev)
 
 	/* Relesing DMA ownership*/
 	intel_adsp_gpdma_release_ownership(dev);
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	/* Power down */
 	return intel_adsp_gpdma_disable(dev);
 #else
 	return 0;
-#endif /* CONFIG_SOC_SERIES_INTEL_ACE */
+#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */
 }
 #endif /* CONFIG_PM_DEVICE */
 
@@ -428,7 +428,7 @@ int intel_adsp_gpdma_get_attribute(const struct device *dev, uint32_t type, uint
 	return 0;
 }
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 static inline void ace_gpdma_intc_unmask(void)
 {
 	ACE_DINT[0].ie[ACE_INTL_GPDMA] = BIT(0);
@@ -449,7 +449,7 @@ int intel_adsp_gpdma_init(const struct device *dev)
 
 	ace_gpdma_intc_unmask();
 
-#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE
+#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	if (pm_device_on_power_domain(dev)) {
 		pm_device_init_off(dev);
 	} else {

diff --git a/drivers/dma/dma_intel_adsp_hda_host_in.c b/drivers/dma/dma_intel_adsp_hda_host_in.c
@@ -49,7 +49,8 @@ static const struct dma_driver_api intel_adsp_hda_dma_host_in_api = {
 			    DEVICE_DT_INST_GET(inst),			\
 			    DT_INST_IRQ(inst, sense));			\
 		irq_enable(DT_INST_IRQN(inst));			\
-		IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE, (ACE_DINT[0].ie[ACE_INTL_HDAHIDMA] = 1;)) \
+		IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE,	\
+			    (ACE_DINT[0].ie[ACE_INTL_HDAHIDMA] = 1;))	\
 	}
 
 DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_IN_INIT)
diff --git a/drivers/dma/dma_intel_adsp_hda_host_out.c b/drivers/dma/dma_intel_adsp_hda_host_out.c
@@ -53,7 +53,8 @@ static const struct dma_driver_api intel_adsp_hda_dma_host_out_api = {
 			    DEVICE_DT_INST_GET(inst),			\
 			    DT_INST_IRQ(inst, sense));			\
 		irq_enable(DT_INST_IRQN(inst));			\
-		IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE, (ACE_DINT[0].ie[ACE_INTL_HDAHODMA] = 1;)) \
+		IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE,	\
+			    (ACE_DINT[0].ie[ACE_INTL_HDAHODMA] = 1;))	\
 	}
 
 DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_OUT_INIT)
diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
@@ -94,7 +94,7 @@ static uint32_t get_hpsram_bank_idx(uintptr_t pa)
  */
 static uint16_t flags_to_tlb_perms(uint32_t flags)
 {
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
+#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 	uint16_t perms = 0;
 
 	if ((flags & SYS_MM_MEM_PERM_RW) == SYS_MM_MEM_PERM_RW) {
@@ -111,7 +111,7 @@ static uint16_t flags_to_tlb_perms(uint32_t flags)
 #endif
 }
 
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
+#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 /**
  * Convert TLB entry permission bits to the SYS_MM_MEM_PERM_* flags.
  *
@@ -136,7 +136,7 @@ static uint16_t tlb_perms_to_flags(uint16_t perms)
 
 static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking)
 {
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
+#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 	if (bank_idx > ace_hpsram_get_bank_count()) {
 		return -1;
 	}
@@ -444,7 +444,7 @@ int sys_mm_drv_page_flag_get(void *virt, uint32_t *flags)
 	ARG_UNUSED(virt);
 	int ret = 0;
 
-#if defined(CONFIG_SOC_SERIES_INTEL_ACE)
+#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 	uint16_t *tlb_entries = UINT_TO_POINTER(TLB_BASE);
 	uint16_t ent;
 

diff --git a/drivers/timer/intel_adsp_timer.c b/drivers/timer/intel_adsp_timer.c
@@ -27,7 +27,7 @@
 
 #define COMPARATOR_IDX  0 /* 0 or 1 */
 
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 #define TIMER_IRQ ACE_IRQ_TO_ZEPHYR(ACE_INTL_TTS)
 #else
 #define TIMER_IRQ DSP_WCT_IRQ(COMPARATOR_IDX)
@@ -198,7 +198,7 @@ static void irq_init(void)
 	 * (for per-core control) above the interrupt controller.
 	 * Drivers need to do that part.
 	 */
-#ifdef CONFIG_SOC_SERIES_INTEL_ACE
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 	ACE_DINT[cpu].ie[ACE_INTL_TTS] |= BIT(COMPARATOR_IDX + 1);
 	sys_write32(sys_read32(DSPWCTCS_ADDR) | ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX),
 			DSPWCTCS_ADDR);

diff --git a/soc/intel/intel_adsp/CMakeLists.txt b/soc/intel/intel_adsp/CMakeLists.txt
@@ -6,7 +6,7 @@
 zephyr_include_directories(common)
 
 add_subdirectory(common)
-if(CONFIG_SOC_SERIES_INTEL_ACE)
+if(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 	zephyr_include_directories(ace)
 	add_subdirectory(ace)
 endif()

diff --git a/soc/intel/intel_adsp/ace/Kconfig b/soc/intel/intel_adsp/ace/Kconfig
@@ -2,7 +2,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_INTEL_ACE
+config SOC_SERIES_INTEL_ADSP_ACE
 	select SOC_FAMILY_INTEL_ADSP
 	select XTENSA
 	select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
@@ -14,10 +14,10 @@ config SOC_SERIES_INTEL_ACE
 	select HAS_PM
 
 config SOC_INTEL_ACE15_MTPM
-	select SOC_SERIES_INTEL_ACE
+	select SOC_SERIES_INTEL_ADSP_ACE
 
 config SOC_INTEL_ACE20_LNL
-	select SOC_SERIES_INTEL_ACE
+	select SOC_SERIES_INTEL_ADSP_ACE
 
 config SOC_INTEL_COMM_WIDGET
 	bool "Intel Communication Widget driver"