soc: espressif: esp32s3: AMP flash support

Rework memory layout and add cache memory. Add ROM segments to APPCPU default.ld. Signed-off-by: Marek Matej <[email protected]>
zephyrproject-rtos · Jan 9, 2025 · 5b65a2f · 5b65a2f
1 parent 3c1dcf3
commit 5b65a2f
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Showing 6 changed files with 243 additions and 118 deletions.
diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c
@@ -63,6 +63,12 @@
 
 #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
 
+#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU)
+#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_partition)
+#else
+#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_appcpu_partition)
+#endif
+
 void __start(void);
 static HDR_ATTR void (*_entry_point)(void) = &__start;
 
@@ -71,14 +77,13 @@ extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
 extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
 
 #ifndef CONFIG_MCUBOOT
-static uint32_t _app_irom_start =
-	(FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_irom_start);
+static uint32_t _app_irom_start = (PART_OFFSET + (uint32_t)&_image_irom_start);
+//	(FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_irom_start);
 static uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
 
-static uint32_t _app_drom_start =
-	(FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_drom_start);
+static uint32_t _app_drom_start = (PART_OFFSET + (uint32_t)&_image_drom_start);
+//	(FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_drom_start);
 static uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
-#endif
 
 static uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr);
 static uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr);
@@ -99,6 +104,7 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 	uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
 	uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
 
+	/* Traverse segments to fix flash offset changes due to post-build processing */
 #ifndef CONFIG_BOOTLOADER_MCUBOOT
 	esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
 	size_t offset = FIXED_PARTITION_OFFSET(boot_partition);
@@ -242,6 +248,7 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 		       app_irom_size);
 	esp_rom_uart_tx_wait_idle(0);
 }
+#endif
 
 void __start(void)
 {
@@ -264,7 +271,7 @@ void __start(void)
 	}
 #endif
 
-#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU) && \
+#if /* !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU) &&*/ \
 	!defined(CONFIG_MCUBOOT)
 	map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_irom_start,
 			 _app_irom_vaddr, _app_irom_size);

diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt
@@ -98,8 +98,6 @@ endif()
 
 if(CONFIG_MCUBOOT)
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-elseif(CONFIG_SOC_ESP32_APPCPU)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "")
 else()
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
 endif()
diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt
@@ -62,7 +62,7 @@ if(CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT)
       -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
       ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
 
-  endif()
+ endif()
 
 endif()
 

diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld
@@ -17,9 +17,25 @@ procpu_dram_end = USER_DRAM_END - APPCPU_SRAM_SIZE;
 procpu_iram_org = SRAM_USER_IRAM_START;
 procpu_iram_len = procpu_iram_end - procpu_iram_org;
 
+procpu_dram_org2 = ORIGIN(dram0_0_seg);
 procpu_dram_org = SRAM1_DRAM_START;
 procpu_dram_len = procpu_dram_end - procpu_dram_org;
 
+/* User available ROM memory segments */
+procpu_irom_end = ICACHE_START + ICACHE_SIZE - APPCPU_ROM_SIZE;
+procpu_drom_end = DCACHE_START + DCACHE_SIZE - APPCPU_ROM_SIZE;
+
+procpu_irom_org = ICACHE_START;
+procpu_irom_len = ICACHE_SIZE - APPCPU_ROM_SIZE;
+
+procpu_drom_org = DCACHE_START;
+procpu_drom_len = DCACHE_SIZE - APPCPU_ROM_SIZE;
+
+#if defined(CONFIG_ESP_SPIRAM)
+procpu_extram_org = DCACHE_START
+procpu_extram_len = CONFIG_ESP_SPIRAM_SIZE
+#endif
+
 /* Aliases */
 #define FLASH_CODE_REGION  irom0_0_seg
 #define RODATA_REGION      drom0_0_seg
@@ -50,8 +66,8 @@ MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   mcuboot_hdr (R):  org = 0x0,  len = 0x20
-  metadata (R):     org = 0x20, len = 0x20
-  FLASH (R):        org = 0x40, len = FLASH_SIZE - 0x40
+  metadata (R):     org = 0x20, len = 0x60
+  FLASH (R):        org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
    * (esp_img_header + (n*esp_seg_headers)) would fit */
@@ -61,17 +77,17 @@ MEMORY
   iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len
   dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len
 
-  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
-  drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
+  irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len
+  drom0_0_seg(R):  org = procpu_drom_org, len = procpu_drom_len
 
   /* The `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
    * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
    */
 #if defined(CONFIG_ESP_SPIRAM)
   /* `ext_[id]ram_seg` and `drom0_0_seg` share the same bus and the address region.
    * A dummy section is used to avoid overlap. See `.ext_ram.dummy` */
-  ext_dram_seg(RW): org = DROM_SEG_ORG, len = (CONFIG_ESP_SPIRAM_SIZE)
-  ext_iram_seg(RX): org = IROM_SEG_ORG, len = (CONFIG_ESP_SPIRAM_SIZE)
+  ext_dram_seg(RW): org = procpu_extram_org, len = procpu_extram_len
+  ext_iram_seg(RX): org = procpu_extram_org, len = procpu_extram_len
 #endif
 
   /* RTC fast memory (executable). Persists over deep sleep.
@@ -139,7 +155,23 @@ SECTIONS
      */
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
-    LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data))
+    LONG(LOADADDR(.dram0.data_end) + SIZEOF(.dram0.data_end) - LOADADDR(.dram0.data))
+
+    LONG(0);
+    LONG(0);
+    LONG(0);
+
+    LONG(0);
+    LONG(0);
+    LONG(0);
+
+    LONG(_image_irom_vaddr);
+    LONG(_image_irom_start);
+    LONG(_image_irom_size);
+
+    LONG(_image_drom_vaddr);
+    LONG(_image_drom_start);
+    LONG(_image_drom_size);
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
@@ -505,8 +537,8 @@ SECTIONS
     /* Spacer section is required to skip .iram0.text area because
      * iram0_0_seg and dram0_0_seg reflect the same address space on different buses.
      */
-    . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START;
-    . = ALIGN(4) + 16;
+    . = ORIGIN(dram0_0_seg) + (MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START);
+    . = ALIGN(16);
   } GROUP_LINK_IN(RAMABLE_REGION)
 
   .dram0.data :
@@ -699,7 +731,7 @@ SECTIONS
   #include <zephyr/linker/common-rom/common-rom-logging.ld>
   #pragma pop_macro("GROUP_ROM_LINK_IN")
 
-  .dram0.end :
+  .dram0.data_end :
   {
     __data_end = ABSOLUTE(.);
     _data_end = ABSOLUTE(.);
-Original file line number
+Diff line change
@@ Expand Up / @@ -62,7 +62,7 @@ if(CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT) @@
           -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
           ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-      endif()
+     endif()
     endif()
@@ Expand Down @@