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Feature/func #42

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6da61db
Add MRS Commmand
hanloveland Apr 7, 2023
348cbf9
Add LRDIMM configuration file (ini file)
hanloveland Apr 11, 2023
cf41d23
Implementation LRDIMM
hanloveland Apr 11, 2023
ee78fbe
Implemenation Timing Parameter related to LRDIMM
hanloveland Apr 13, 2023
857c175
Add Data Path from MC to DRAM (only support LRDIMM)
hanloveland Apr 24, 2023
4c12414
Add Custom CPU to generate memory request with real Data
hanloveland Apr 26, 2023
88ce925
add Datareshape function, mergedaddress function
gkstnwls0 May 24, 2023
79a104e
Delete .vscode directory
hanloveland May 24, 2023
e773db9
Delete dramsim3.json
hanloveland May 24, 2023
cbe414d
clean code
hanloveland May 24, 2023
66dbdf4
Implementation of bit swap between DIMM Module and DRAM
hanloveland May 25, 2023
a19eb19
wr_DQ_remapping function, rd_DQ_remapping function modify
gkstnwls0 Jun 1, 2023
ea2aeef
wr_DQ_remapping function, rd_DQ_remapping function modify
gkstnwls0 Jun 2, 2023
2834f5f
Merge pull request #1 from hanloveland/feature/func
hanloveland Jun 2, 2023
99decaf
Fix Buffer on Board and Make DQ Mapping Variable of BoB shared with c…
hanloveland Jun 7, 2023
95d6fc3
Add Display Function at address structure for debug
hanloveland Jun 7, 2023
8f60908
Add MergedAddress Function that take address structure
hanloveland Jun 7, 2023
55fb970
Add NDP-related Functions
hanloveland Jun 7, 2023
3269ffa
Clean Code & Rearrage for code readability
hanloveland Jun 8, 2023
d95caa1
Add FP16 structure(FP32 <-> FP16 conversion and arithmetic operations…
gkstnwls0 Jun 9, 2023
e96c3eb
Merge pull request #2 from hanloveland/feature/func
hanloveland Jun 9, 2023
ea2ca8d
Merge pull request #3 from hanloveland/dev
hanloveland Jun 9, 2023
e983abd
Clean Code
hanloveland Jun 12, 2023
c064348
remove duplicated functions
hanloveland Jun 12, 2023
fbcf62a
Merge pull request #4 from hanloveland/dev
hanloveland Jun 12, 2023
6dd2f5a
Bug Fix
hanloveland Jun 13, 2023
b2ecc17
Fix Address Incremental Order
hanloveland Jun 13, 2023
b544bd5
Merge pull request #5 from hanloveland/dev
hanloveland Jun 13, 2023
f8ee9ea
merge2
gkstnwls0 Jun 16, 2023
95a37a1
Add convert data format function(FP32 <-> FP16) to custom_cpu.cc
gkstnwls0 Jun 21, 2023
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10 changes: 0 additions & 10 deletions .vscode/.cmaketools.json

This file was deleted.

70 changes: 0 additions & 70 deletions .vscode/launch.json

This file was deleted.

6 changes: 0 additions & 6 deletions .vscode/settings-backup.json

This file was deleted.

12 changes: 0 additions & 12 deletions .vscode/tasks.json

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7 changes: 7 additions & 0 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,9 @@ add_library(dramsim3 SHARED
src/simple_stats.cc
src/timing.cc
src/memory_system.cc
src/bob.cc
src/custom_cpu.cc
src/ndp_address_table.cc
)

if (THERMAL)
Expand Down Expand Up @@ -71,6 +74,10 @@ if (CMD_TRACE)
target_compile_options(dramsim3 PRIVATE -DCMD_TRACE)
endif (CMD_TRACE)

if (MY_DEBUG)
target_compile_options(dramsim3 PRIVATE -DMY_DEBUG)
endif (MY_DEBUG)

if (ADDR_TRACE)
target_compile_options(dramsim3 PRIVATE -DADDR_TRACE)
endif (ADDR_TRACE)
Expand Down
19 changes: 14 additions & 5 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,23 +2,32 @@

CC=gcc
CXX=g++

MY_DEBUG=0
EN_CMD_TRACE=0
FMT_LIB_DIR=ext/fmt/include
INI_LIB_DIR=ext/headers
JSON_LIB_DIR=ext/headers
ARGS_LIB_DIR=ext/headers

INC=-Isrc/ -I$(FMT_LIB_DIR) -I$(INI_LIB_DIR) -I$(ARGS_LIB_DIR) -I$(JSON_LIB_DIR)
CXXFLAGS=-Wall -O3 -fPIC -std=c++11 $(INC) -DFMT_HEADER_ONLY=1

#CXXFLAGS=-Wall -O3 -fPIC -std=c++11 $(INC) -DFMT_HEADER_ONLY=1
CXXFLAGS=-Wall -g -fPIC -std=c++11 $(INC) -DFMT_HEADER_ONLY=1
ifeq (${MY_DEBUG},1)
CXXFLAGS+=-DMY_DEBUG
endif
ifeq (${EN_CMD_TRACE},1)
CXXFLAGS+=-DCMD_TRACE
endif
LIB_NAME=libdramsim3.so
EXE_NAME=dramsim3main.out

SRCS = src/bankstate.cc src/channel_state.cc src/command_queue.cc src/common.cc \
src/configuration.cc src/controller.cc src/dram_system.cc src/hmc.cc \
src/memory_system.cc src/refresh.cc src/simple_stats.cc src/timing.cc
src/memory_system.cc src/refresh.cc src/simple_stats.cc src/timing.cc \
src/bob.cc


EXE_SRCS = src/cpu.cc src/main.cc
EXE_SRCS = src/ndp_address_table.cc src/custom_cpu.cc src/cpu.cc src/main.cc

OBJECTS = $(addsuffix .o, $(basename $(SRCS)))
EXE_OBJS = $(addsuffix .o, $(basename $(EXE_SRCS)))
Expand Down
69 changes: 69 additions & 0 deletions configs/DDR4_8Gb_x4_3200_LRDIMM.ini
Original file line number Diff line number Diff line change
@@ -0,0 +1,69 @@
[dram_structure]
protocol = DDR4
bankgroups = 4
banks_per_group = 4
rows = 131072
columns = 1024
device_width = 4
BL = 8

[timing]
tCK = 0.63
AL = 0
CL = 22
CWL = 16
tRCD = 22
tRP = 22
tRAS = 52
tRFC = 560
tRFC2 = 416
tRFC4 = 256
tREFI = 12480
tRPRE = 1
tWPRE = 1
tRRD_S = 4
tRRD_L = 8
tWTR_S = 4
tWTR_L = 12
tFAW = 16
tWR = 24
tWR2 = 25
tRTP = 12
tCCD_S = 4
tCCD_L = 8
tCKE = 8
tCKESR = 9
tXS = 576
tXP = 10
tRTRS = 1

[power]
VDD = 1.2
IDD0 = 52
IPP0 = 3.0
IDD2P = 25
IDD2N = 37
IDD3P = 38
IDD3N = 47
IDD4W = 130
IDD4R = 143
IDD5AB = 250
IDD6x = 30

[system]
channel_size = 98304
channels = 1
bus_width = 64
address_mapping = rochrababgco
queue_structure = PER_BANK
refresh_policy = RANK_LEVEL_STAGGERED
row_buf_policy = OPEN_PAGE
cmd_queue_size = 8
trans_queue_size = 32
is_LRDIMM = true
ranks_per_dimm = 4

[other]
epoch_period = 1587301
output_level = 1

1 change: 1 addition & 0 deletions dramsim3.json
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
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