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110 Open 216 Closed
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Issues list

verilator fails to compile small Example
#742 opened Feb 24, 2017 by oharboe
Queue is not getting synthesized
#737 opened Oct 19, 2016 by preyas3359
abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure
#730 opened Sep 12, 2016 by drom
Exception: sbt.TrapExitSecurityException
#729 opened Sep 12, 2016 by drom
2
Support bulk connects in when?
#727 opened Sep 3, 2016 by jkorinth
Uninferrable width on reg after using fromBits
#726 opened Aug 31, 2016 by da-steve101
RegUpdate and RegReset?
#724 opened Aug 15, 2016 by cornytrace
3
firrtl_interpreter/Concrete.scala: randomSInt produces out of bounds value.
#723 opened Aug 4, 2016 by stevenmburns
2
OrderedDecoupledHWIOTester doesn't report error when compare failed
#716 opened Jul 4, 2016 by songmaotian
Will OrderedDecoupledHWIOTester insert bubble for the output.ready signal?
#715 opened Jul 2, 2016 by songmaotian
2
val differs from expression after assignment
#713 opened Jun 1, 2016 by pw-gecos
Verilog doesn't useelse so memory not inferred as RAM
#709 opened May 23, 2016 by sclukey
2
Cautionary Tale -- Chisel/ISE issue
#707 opened May 18, 2016 by shunshou
3
Inconsistent member names in C++ emulator
#706 opened May 17, 2016 by kenmcmil
Java Exception (and useless error message) on a Reg of Vec of size 0
#703 opened May 12, 2016 by ccelio
Flag to enable warnings for any modules with any unconnected ports
#702 opened May 11, 2016 by ascenium
1
Use of "config" as a Chisel value name results in syntax error in Verilog output
#701 opened May 4, 2016 by ascenium
Bulk connects do not override bundle components
#699 opened Apr 28, 2016 by colinschmidt
4
Catting a UInt of width 0 leads to strange sim results
#697 opened Apr 26, 2016 by da-steve101
1
Compilation Error when assigning from other clock
#696 opened Apr 25, 2016 by da-steve101
4
(Relevant to Enum:) Uppercase identifiers assumed to be stable identifiers in extractor/unapply context Documentation Syntax
#694 opened Apr 15, 2016 by sdtwigg
Testers Vec size issue: java.lang.IndexOutOfBoundsException
#692 opened Apr 13, 2016 by hqjenny
2
Chisel.TestApplicationException: test application exit - exit code 139
#689 opened Apr 11, 2016 by ascenium
4
Warning message needed?
#686 opened Mar 26, 2016 by da-steve101
Cocotb directives in Verilog backend
#674 opened Mar 10, 2016 by Martoni
2
ProTip! Exclude everything labeled bug with -label:bug.