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Add WithUniformBusFrequencies | Fix UARTTSI HarnessBinder #2025

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merged 4 commits into from
Aug 29, 2024
Merged

Add WithUniformBusFrequencies | Fix UARTTSI HarnessBinder #2025

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a46bb1e
Add UniformBusFreq config fragment
jerryz123 Aug 28, 2024
98dcaed
Remove LBWIFRocketConfig - this is now ChipLikeRocketConfig
jerryz123 Aug 28, 2024
4f24d04
Fix WithSimUARTToUARTTSI HBinder
jerryz123 Aug 28, 2024
8395a6f
Rename WithUniformBusFreq to WithUniformBusFreqs
jerryz123 Aug 28, 2024
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6 changes: 1 addition & 5 deletions fpga/src/main/scala/arty/Configs.scala
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Expand Up @@ -24,11 +24,7 @@ class WithArtyTweaks extends Config(

new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithUniformBusFrequencies(32) ++
new testchipip.serdes.WithNoSerialTL ++
new testchipip.soc.WithNoScratchpads
)
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7 changes: 1 addition & 6 deletions fpga/src/main/scala/arty100t/Configs.scala
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Expand Up @@ -33,12 +33,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
new chipyard.config.WithFrontBusFrequency(freqMHz) ++
new chipyard.config.WithSystemBusFrequency(freqMHz) ++
new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
new chipyard.config.WithControlBusFrequency(freqMHz) ++
new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.config.WithUniformBusFrequencies(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
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7 changes: 1 addition & 6 deletions fpga/src/main/scala/nexysvideo/Configs.scala
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Expand Up @@ -29,12 +29,7 @@ class WithNexysVideoTweaks(freqMHz: Double = 50) extends Config(
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
new chipyard.config.WithFrontBusFrequency(freqMHz) ++
new chipyard.config.WithSystemBusFrequency(freqMHz) ++
new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
new chipyard.config.WithControlBusFrequency(freqMHz) ++
new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
new chipyard.config.WithUniformBusFrequencies(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
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6 changes: 1 addition & 5 deletions fpga/src/main/scala/vc707/Configs.scala
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Expand Up @@ -42,11 +42,7 @@ class WithVC707Tweaks extends Config (
// clocking
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithUniformBusFrequencies(50.0) ++

new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq
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6 changes: 1 addition & 5 deletions fpga/src/main/scala/vcu118/Configs.scala
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Expand Up @@ -44,11 +44,7 @@ class WithVCU118Tweaks extends Config(
// clocking
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(100) ++
new chipyard.config.WithSystemBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithUniformBusFrequencies(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
// harness binders
new WithUART ++
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7 changes: 1 addition & 6 deletions generators/chipyard/src/main/scala/config/ChipConfigs.scala
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Expand Up @@ -102,12 +102,7 @@ class ChipBringupHostConfig extends Config(
// Set up clocks of the bringup system
//=============================
new chipyard.clocking.WithPassthroughClockGenerator ++ // pass all the clocks through, since this isn't a chip
new chipyard.config.WithFrontBusFrequency(75.0) ++ // run all buses of this system at 75 MHz
new chipyard.config.WithMemoryBusFrequency(75.0) ++
new chipyard.config.WithPeripheryBusFrequency(75.0) ++
new chipyard.config.WithSystemBusFrequency(75.0) ++
new chipyard.config.WithControlBusFrequency(75.0) ++
new chipyard.config.WithOffchipBusFrequency(75.0) ++
new chipyard.config.WithUniformBusFrequencies(75.0) ++ // run all buses of this system at 75 MHz

// Base is the no-cores config
new chipyard.NoCoresConfig)
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13 changes: 1 addition & 12 deletions generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
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Expand Up @@ -50,15 +50,6 @@ class MMIORocketConfig extends Config(
new freechips.rocketchip.rocket.WithNHugeCores(1) ++
new chipyard.config.AbstractConfig)

class LBWIFRocketConfig extends Config(
new chipyard.config.WithOffchipBusFrequency(500) ++
new testchipip.soc.WithOffchipBusClient(MBUS) ++
new testchipip.soc.WithOffchipBus ++
new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.rocket.WithNHugeCores(1) ++
new chipyard.config.AbstractConfig)

// DOC include start: DmiRocket
class dmiRocketConfig extends Config(
new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl
Expand Down Expand Up @@ -97,8 +88,6 @@ class ManyPeripheralsRocketConfig extends Config(
class UARTTSIRocketConfig extends Config(
new chipyard.harness.WithSerialTLTiedOff ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.config.WithMemoryBusFrequency(10) ++
new chipyard.config.WithFrontBusFrequency(10) ++
new chipyard.config.WithPeripheryBusFrequency(10) ++
new chipyard.config.WithUniformBusFrequencies(2) ++
new freechips.rocketchip.rocket.WithNHugeCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig)
7 changes: 1 addition & 6 deletions generators/chipyard/src/main/scala/config/SpikeConfigs.scala
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Expand Up @@ -25,12 +25,7 @@ class SpikeFastUARTConfig extends Config(
new chipyard.WithNSpikeCores(1) ++
new chipyard.config.WithUART(txEntries=128, rxEntries=128) ++ // Spike sim requires a larger UART FIFO buffer,
new chipyard.config.WithNoUART() ++ // so we overwrite the default one
new chipyard.config.WithPeripheryBusFrequency(2) ++ // configured to be as fast as possible
new chipyard.config.WithMemoryBusFrequency(2) ++
new chipyard.config.WithControlBusFrequency(2) ++
new chipyard.config.WithSystemBusFrequency(2) ++
new chipyard.config.WithFrontBusFrequency(2) ++
new chipyard.config.WithOffchipBusFrequency(2) ++
new chipyard.config.WithUniformBusFrequencies(2) ++ // configured to be as fast as possible
new chipyard.config.AbstractConfig)

// No L2 and a ludicrous L1D
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5 changes: 1 addition & 4 deletions generators/chipyard/src/main/scala/config/TracegenConfigs.scala
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Expand Up @@ -15,10 +15,7 @@ class AbstractTraceGenConfig extends Config(
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
new chipyard.config.WithTracegenSystem ++
new chipyard.config.WithNoSubsystemClockIO ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new chipyard.config.WithUniformBusFrequencies(1000.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.groundtest.GroundTestBaseConfig)

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8 changes: 8 additions & 0 deletions generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
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Expand Up @@ -110,6 +110,14 @@ class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) =
class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
})
class WithUniformBusFrequencies(freqMHz: Double) extends Config(
new WithPeripheryBusFrequency(freqMHz) ++
new WithSystemBusFrequency(freqMHz) ++
new WithFrontBusFrequency(freqMHz) ++
new WithControlBusFrequency(freqMHz) ++
new WithOffchipBusFrequency(freqMHz) ++
new WithMemoryBusFrequency(freqMHz)
)

class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
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6 changes: 3 additions & 3 deletions generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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Expand Up @@ -270,9 +270,9 @@ class WithDriveChipIdPin extends HarnessBinder({
})

class WithSimUARTToUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
UARTAdapter.connect(Seq(port.io),
baudrate=port.io.c.initBaudRate,
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
UARTAdapter.connect(Seq(port.io.uart),
baudrate=port.io.uart.c.initBaudRate,
clockFrequency=th.getHarnessBinderClockFreqHz.toInt,
forcePty=true)
}
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