Bump Spike

[jerryz123]

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[abejgonzalez]

While we are at it, can you also update the SpikeTile ISA to have zvl128b_zve64d and zicsr_zifencei_zihpm (to match Rocket) (so something like this: rv64imafdvczicsr_zifencei_zihpm_zvl128b_zve64d).

I also want these two PRs in for checkpointing: riscv-software-src/riscv-isa-sim#1715 riscv-software-src/riscv-isa-sim#1714 but I can re-bump later

[jerryz123]

Rocket does not currently have Zvl/Zve, are you sure you want them in SpikeTile?

[abejgonzalez]

Rocket does not currently have Zvl/Zve, are you sure you want them in SpikeTile?

SpikeTiles current ISA is "rv64gcv_Zfh". I don't need V, but I figured you put V in there in the past to support it for some reason.

[jerryz123]

Oh right. You are right then, we should put the full isa str

[abejgonzalez]

Thanks for the SpikeTile fix