[ci skip] Re-add suggestName for axi4 mmio mem

ucb-bar · Oct 14, 2023 · 6bd2e9d · 6bd2e9d
1 parent deab3b1
commit 6bd2e9d
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -135,7 +135,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
 class WithSimAXIMMIO extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: AXI4MMIOPort) => {
     val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty))
-    withClock(port.io.clock) { Module(mmio_mem.module) }
+    withClock(port.io.clock) { Module(mmio_mem.module).suggestName("mmio_mem") }
     mmio_mem.io_axi4.head <> port.io.bits
   }
 })