Fix unassigned clocks due to removing implicit clock from BaseSubsystem

ucb-bar · Oct 19, 2023 · 1d9dba5 · 1d9dba5
1 parent 686d9a5
commit 1d9dba5
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Showing 9 changed files with 15 additions and 11 deletions.
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -36,8 +36,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
 
   // Set up clock domain
   private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
-  val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
-  prci_ctrl_domain.clockNode := tlbus.fixedClockNode
+  val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
 
   val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar

diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -55,6 +55,7 @@ class AbstractConfig extends Config(
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
+  new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
 
   new testchipip.WithCustomBootPin ++                               // add a custom-boot-pin to support pin-driven boot address

diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -199,12 +199,13 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
 trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
   val streamingFIR = p(GenericFIRKey) match {
     case Some(params) => {
-      val streamingFIR = LazyModule(new TLGenericFIRChain(
+      val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
+      val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
         genIn = FixedPoint(8.W, 3.BP),
         genOut = FixedPoint(8.W, 3.BP),
         coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)),
-        params = params))
-      pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
+        params = params)) }
+      pbus.coupleTo("streamingFIR") { domain { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ }
       Some(streamingFIR)
     }
     case None => None

diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -131,8 +131,9 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
 trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
   val passthrough = p(StreamingPassthroughKey) match {
     case Some(params) => {
-      val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
-      pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
+      val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
+      val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
+      pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
       Some(streamingPassthroughChain)
     }
     case None => None

diff --git a/generators/fft-generator b/generators/fft-generator
diff --git a/generators/icenet b/generators/icenet
diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/testchipip b/generators/testchipip
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
@@ -26,6 +26,8 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
   lazy val clintOpt = None
   lazy val debugOpt = None
   lazy val plicOpt = None
+  lazy val clintDomainOpt = None
+  lazy val plicDomainOpt = None
 
   override lazy val module = new TraceGenSystemModuleImp(this)
 }
+2 −3		src/main/scala/devices/debug/Custom.scala
+3 −0		src/main/scala/devices/debug/Debug.scala
+1 −3		src/main/scala/devices/tilelink/BootROM.scala
+12 −13		src/main/scala/devices/tilelink/CLINT.scala
+6 −8		src/main/scala/devices/tilelink/Plic.scala
+1 −1		src/main/scala/diplomacy/BundleBridge.scala
+5 −1		src/main/scala/diplomacy/LazyModule.scala
+2 −0		src/main/scala/groundtest/GroundTestSubsystem.scala
+1 −1		src/main/scala/interrupts/Crossing.scala
+1 −1		src/main/scala/interrupts/Xbar.scala
+1 −0		src/main/scala/prci/ClockDomain.scala
+1 −0		src/main/scala/subsystem/Configs.scala
+6 −4		src/main/scala/subsystem/HasHierarchicalElements.scala
+5 −3		src/main/scala/subsystem/HasTiles.scala
+1 −1		src/main/scala/subsystem/InterruptBus.scala
+17 −15		src/main/scala/subsystem/RTC.scala
+5 −0		src/main/scala/tilelink/BusWrapper.scala
+1 −4		src/main/scala/BlockDevice.scala
+1 −2		src/main/scala/TileResetCtrl.scala