This project serves as PCB bringup for the Sirius chip taped-out in 2024 Q3, Intel16 USP. Sirius (binary star) is a pair of 4x4
| Task | Start Date | Duration |
|---|---|---|
| Forking from Cygnus and pin remapping | 2025-1-26 | - |
- $550
- Artix 7
- USB-UART / Ethernet / FT2232 (FTDI USB-FIFO chip, kind of an old part with iffy drivers)
- 512 MiB DDR3
- FMC-LPC (ASP-134603-01), 34x2 pins, Vadj set to 1.2V by default, easy
- Used by Maveric Bringup
- One for each chiplet
- Q3 of the socket corresponds to the Golden Triangle (Pin 1 mark)
- Socket quandrant order should look identical as U1
| Socket | Chip |
|---|---|
| Q1 | U2 Q3+Q4 |
| Q2 | U1 Q1+Q2 |
| Q3 | U2 Q1+Q2 |
| Q4 | U1 Q3+Q4 |
| Net | Signal Name | Description |
|---|---|---|
| VDD_U1 | Chiplet 1 digital supply | 0.85 V nominal, generated by bench power supply through banana connector or LDO |
| VDD_U2 | Chiplet 2 digital supply | 0.85 V nominal, generated by bench power supply through banana connector or LDO |
| IO | IO cell supply | 1.2 V, generated by bench power supply through banana connector or LDO |
| VDD_PRE_U1 | Chiplet 1 DDR precharge supply | expected 0.6 V, generated by bench power supply through banana connector |
| VDDQ_U1 | Chiplet 1 DDR PHY supply | expected 1.2 V, generated by bench power supply through banana connector |
| DLL_VINIT_U1 | Chiplet 1 DLL backup supply | boot the DLL in a) case of jumpstarting DLL locking due to false lock conditions and b) booting DLL in case of total system failure |
| DLL_IBIAS_MAIN_U1 | Chiplet 1 DLL analog bias current | This bump is used to supply a bias current to all the circuits in the analog section |
| GND | Ground | Single ground shorted together |
There's two LDOs on board that converts 3.3 V from FMC to 1.2 V and 0.85 V. The LDO is capable of 1A output.
Core clock (clock_u1, clock_u2)
- 100 MHz nominal slow clock, driven by external clock generator.
- 1.2 Vpp
- 50 Ohm impedance
- 50R termination resistor near chip socket
- feed in through SMA connector
PLL refclk (pll_refclk_u1, pll_refclk_u2)
- 100 MHz nominal input, 1.2 Vpp
- 1.2 Vpp
- 50 Ohm impedance
- 50R termination resistor near chip socket
- feed in through SMA connector
Debug clock (clk_debug_u1, clk_debug_u1)
- PLL tap debug clock out, can be muxed to output other clocks
- feed out through 2.54 mm pin header.
UCIe clock
- 8GHz differential
- Used to drive the UCIe interface
Chip reset is active high (TODO: confirm this)
Reset can be selected by a pin header jumper to use either button or FMC connection
Low priority low speed signal, route to pin header directly. Use off-board level shifter.
Follows the FT-LINK condensed pin map.
Configurable pin header selector to route to either 3.3V pin header or 1.2 V FMC.
Using the same level shifter design as Maveric.
Configurable resistor bank to route to either FMC or debug header. The resistor selectors are by default all placed, so we can monitor FMC traffic through the pin header.
If signal integrity is a concern, we can remove the pin header selectors manually.
Configurable pin header jumper selector to connect to FMC.
If manual control of the signal voltage is needed, need to use jumper cable to tie signals to either high or low. Since this is configured before chip bootup and will not change during the chip execution, this is fine.
A pin header selector to tie signal high or low.
All DDR digital signals broke out to a pin header. This is only present for chip U1.
| Signal | FMC Net Name | FMC Pin | FPGA Pin (Nexys Video) | Notes |
|---|---|---|---|---|
| serial_tl_clock | LA_00_P_CC | G6 | ||
| serial_tl_in_valid | LA_03_P | G9 | ||
| serial_tl_in_ready | LA_08_P | G12 | ||
| serial_tl_in_bits[0] | LA_12_P | G15 | ||
| serial_tl_out_valid | LA_02_P | H7 | ||
| serial_tl_out_ready | LA_04_P | H10 | ||
| serial_tl_out_bits[0] | LA_07_P | H13 | ||
| uart_rx | LA_20_P | G21 | selectable | |
| uart_tx | LA_20_N | G22 | selectable | |
| reset | LA_25_P | G27 | selectable | |
| ucie_sel_fmc | LA_29_P | G30 | selectable, only present for U1 | |
| ucie_sel_fmc | LA_29_N | G31 | selectable, only present for U1 |
8 layer PCBs
| Index | Layer Name | Purpose |
|---|---|---|
| 1 | L1 | High Speed Signals, DDR + Clock + SerialTL, U1 |
| 2 | L2 | GND |
| 3 | L3 | Low Speed Signals, U1 + U2 |
| 4 | L4 | GND |
| 5 | L5 | VDD_IO (polygon/trace) + VDD_core for U2 |
| 6 | L6 | VDD_pre + VDDQ + other DDR |
| 7 | L7 | GND |
| 8 | L8 | VDD_core for U1 |
| 9 | L9 | GND |
| 10 | L10 | High Speed Signals, DDR + Clock + SerialTL, U2 |
GND: add stiching between the 4 ground layers
Stackup: JLC10121H-2116
Layout will be done in millimeters (mm)
Regarding JLC layout service: not optimal, since it's priced by pad count, and we have a lot of powers and grounds
FMC indentation is at the bottom, which matches the FPGA.
For core and IO power, wide trace on top layer to connect pins together, and then via down as much as possible
Decoupling capacitors at the bottom layer, with mechanical clearance to the backplate pattern.
VDD_IO net
DDL_IBAS need a narrow trace to connect to pin
using calculated 50R trace, 0.186 mm, diff routing to SMA receivers
Due to signal congestion, had to disconnect 1 VDD_IO pin and 2 GND pin.
SMA directly to pin, with 50R resistor placed close to socket.
need to use both L3 and L10 layer
Entire board is GND stiched with 4mm spacing vias.
12 DRCs are due to banana connector silkscreen out of board, which is fine.
1 DRC is FMC connector silkscreen too close to the mechanical hole, which is fine.
Design the bumpmap / interposer with PCB routing in mind! Put high speed signals or nets that require wide traces around the edge of the pin map.