Merge pull request YosysHQ#694 from YosysHQ/gatecat/interchange-glbroute

interchange: Initial global routing implementation
timvideos · May 7, 2021 · 432b9d8 · 432b9d8
2 parents 3144e83 + 51949d9
commit 432b9d8
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Showing 5 changed files with 337 additions and 2 deletions.
diff --git a/.github/workflows/interchange_ci.yml b/.github/workflows/interchange_ci.yml
@@ -108,7 +108,7 @@ jobs:
       env:
         RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
         PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
-        PYTHON_INTERCHANGE_TAG: v0.0.11
+        PYTHON_INTERCHANGE_TAG: v0.0.12
         PRJOXIDE_REVISION: b5d88c3491770559c3c10cccb1651db65ab061b1
         DEVICE: ${{ matrix.device }}
       run: |

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
@@ -479,6 +479,32 @@ IdString Arch::getWireType(WireId wire) const
     return IdString(chip_info->wire_types[wire_type].name);
 }
 
+bool Arch::is_site_wire(WireId wire) const
+{
+    if (wire.tile == -1)
+        return false;
+    const auto &tile_type = loc_info(chip_info, wire);
+    return tile_type.wire_data[wire.index].site != -1;
+}
+
+WireCategory Arch::get_wire_category(WireId wire) const
+{
+    int tile = wire.tile, index = wire.index;
+    if (tile == -1) {
+        // Nodal wire
+        const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
+        tile = wr.tile;
+        index = wr.index;
+    }
+    auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
+    if (index >= w2t.ssize())
+        return WIRE_CAT_GENERAL;
+    int wire_type = w2t[index];
+    if (wire_type == -1)
+        return WIRE_CAT_GENERAL;
+    return WireCategory(chip_info->wire_types[wire_type].category);
+}
+
 std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
 
 // -----------------------------------------------------------------------
@@ -773,6 +799,8 @@ bool Arch::place()
     getCtx()->check();
 #endif
 
+    place_globals();
+
     std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
     if (placer == "heap") {
         PlacerHeapCfg cfg(getCtx());
@@ -895,6 +923,8 @@ bool Arch::route()
     // terminate at a BEL pin.
     disallow_site_routing = true;
 
+    route_globals();
+
     bool result;
     if (router == "router1") {
         result = router1(getCtx(), Router1Cfg(getCtx()));

diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
@@ -533,6 +533,9 @@ struct Arch : ArchAPI<ArchRanges>
         return range;
     }
 
+    bool is_site_wire(WireId wire) const;
+    WireCategory get_wire_category(WireId wire) const;
+
     // -------------------------------------------------
 
     PipId getPipByName(IdStringList name) const final;
@@ -686,6 +689,11 @@ struct Arch : ArchAPI<ArchRanges>
                       std::unordered_set<CellInfo *> *placed_cells);
     void pack_ports();
     void decode_lut_cells();
+
+    const GlobalCellPOD *global_cell_info(IdString cell_type) const;
+    void place_globals();
+    void route_globals();
+
     bool pack() final;
     bool place() final;
     bool route() final;

diff --git a/fpga_interchange/chipdb.h b/fpga_interchange/chipdb.h
@@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
  * kExpectedChipInfoVersion
  */
 
-static constexpr int32_t kExpectedChipInfoVersion = 8;
+static constexpr int32_t kExpectedChipInfoVersion = 9;
 
 // Flattened site indexing.
 //
@@ -320,6 +320,18 @@ NPNR_PACKED_STRUCT(struct WireTypePOD {
     int32_t category; // WireCategory
 });
 
+NPNR_PACKED_STRUCT(struct GlobalCellPinPOD {
+    int32_t name;     // constid
+    int16_t max_hops; // max routing hops to try
+    int8_t guide_placement;
+    int8_t force_routing;
+});
+
+NPNR_PACKED_STRUCT(struct GlobalCellPOD {
+    int32_t cell_type;
+    RelSlice<GlobalCellPinPOD> pins;
+});
+
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<char> name;
     RelPtr<char> generator;
@@ -333,6 +345,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelSlice<NodeInfoPOD> nodes;
     RelSlice<PackagePOD> packages;
     RelSlice<WireTypePOD> wire_types;
+    RelSlice<GlobalCellPOD> global_cells;
 
     // BEL bucket constids.
     RelSlice<int32_t> bel_buckets;